Loading data for iterative evaluation through SIMD registers
US-10162603-B2 · Dec 25, 2018 · US
Caching of specific data in cache memory
Caching of specific data in cache memory · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F2212/45 |
| Official title | Caching of specific data in cache memory |
| Display label | Caching of specific data in cache memory |
| Total patents | 226 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is growing.
| Year | Patents |
|---|---|
| 2015 | 20 |
| 2016 | 16 |
| 2017 | 23 |
| 2018 | 30 |
| 2019 | 23 |
| 2020 | 20 |
| 2021 | 10 |
| 2022 | 17 |
| 2023 | 19 |
| 2024 | 26 |
| 2025 | 19 |
| 2026 | 3 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Data managment for cache memory
US-9798672-B1 · Oct 24, 2017 · US
Selecting a resource from a set of resources for performing an operation
US-9766936-B2 · Sep 19, 2017 · US
Operating a FIFO memory
US-9767034-B2 · Sep 19, 2017 · US
In-memory interconnect protocol configuration registers
US-9767028-B2 · Sep 19, 2017 · US
Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device
US-9747041-B2 · Aug 29, 2017 · US
Distributed history buffer flush and restore handling in a parallel slice design
US-9747217-B2 · Aug 29, 2017 · US
Distributed history buffer flush and restore handling in a parallel slice design
US-9740620-B2 · Aug 22, 2017 · US
Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods
US-9740621-B2 · Aug 22, 2017 · US
Replicating test case data into a cache with non-naturally aligned data boundaries
US-2017220442-A1 · Aug 3, 2017 · US
Replicating test case data into a cache with non-naturally aligned data boundaries
US-2017220438-A1 · Aug 3, 2017 · US
Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device
US-2017185315-A1 · Jun 29, 2017 · US
Memory access control device, cache memory and semiconductor device
US-9684602-B2 · Jun 20, 2017 · US
Migration of Data to Register File Cache
US-2017168949-A1 · Jun 15, 2017 · US
Increased cache performance with multi-level queues of complete tracks
US-9665493-B2 · May 30, 2017 · US
Tile-Based Graphics
US-2017148130-A1 · May 25, 2017 · US
Medical device user caching
US-2017140134-A1 · May 18, 2017 · US
In-memory interconnect protocol configuration registers
US-2017123987-A1 · May 4, 2017 · US
Visibility Parameters for an In-Memory Cache
US-2017116130-A1 · Apr 27, 2017 · US
Migration of data to register file cache
US-9612968-B2 · Apr 4, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F2212/45?
- CPC G06F2212/45 is the Cooperative Patent Classification code for “Caching of specific data in cache memory.”
- How many patents are filed under CPC G06F2212/45 (Caching of specific data in cache memory)?
- Our database includes 226 publications tagged with this CPC code.
- Is patent activity under CPC G06F2212/45 growing?
- Publication counts under this code: 26 in 2024 vs 19 in 2025 (latest complete years).