Increased cache performance with multi-level queues of complete tracks

Patent metadata

Field	Value
Publication number	US-9665493-B2
Application number	US-201414505702-A
Country	US
Kind code	B2
Filing date	Oct 3, 2014
Priority date	Oct 3, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

Exemplary method, system, and computer program product embodiments for increased cache performance using multi-level queues by a processor device. The method includes distributing to each one of a plurality of central processing units (CPUs) workload operations for creating complete tracks from partial tracks, creating sub-queues of the complete tracks for distributing to each one of the CPUs, and creating demote scan tasks based on workload of the CPUs. Additional system and computer program product embodiments are disclosed and provide related advantages.

First claim

The invention claimed is:

1. A method for increased cache performance efficiency by a processor device in a computing environment, the method comprising:
distributing to each one of a plurality of central processing units (CPUs) workload operations for creating complete cache tracks from partial cache tracks by creating a complete cache track queue and a partial cache track pointer without a lock by each one of the CPUs;
using, by each one of the CPUs, an assembler queue to accumulate each of the complete cache tracks from the partial cache tracks including using a pointer copy of a partial cache track to assemble a complete cache track, the assembler queue sending each of the complete cache tracks to the complete cache track queue;
creating sub-queues in front of each of the assembler queues accumulating the complete cache tracks, the sub-queues including both an append queue and a build queue, wherein the build queue fills the append queue using segments from the partial cache track pointer copy combined with a partial cache track and the append queue fills the assembler queue; and
creating and throttling a plurality of demote scan tasks to continuously maintain pace with the filling of the complete cache track queue, the assembler queue, and the sub-queues.

2. The method of claim 1 , further including using a reclaim task to fill the build queue.

3. The method of claim 1 , further including maintaining the plurality of demote scan tasks by adding or removing task control blocks (TCB) according to a number of allocation requests.

4. A system for increased creased cache performance efficiency in a computing environment, the system comprising:
at least one processor device operable in the computing storage environment, wherein the at least one processor device:
distributes to each one of a plurality of central processing units (CPUs) workload operations for creating complete cache tracks from partial cache tracks by creating a complete cache track queue and a partial cache track pointer without a lock by each one of the CPUs,
uses, by each one of the CPUs, an assembler queue to accumulate each of the complete cache tracks from the partial cache tracks including using a pointer copy of a partial cache track to assemble a complete cache track, the assembler queue sending each of the complete cache tracks to the complete cache track queue,
creates sub-queues in front of each of the assembler queues accumulating the complete cache tracks, the sub-queues including both an append queue and a build queue, wherein the build queue fills the append queue using segments from the partial cache track pointer copy combined with a partial cache track and the append queue fills the assembler queue, and
creates and throttles a plurality of demote scan tasks to continuously maintain pace with the filling of the complete cache track queue, the assembler queue, and the sub-queues.

5. The system of claim 4 , wherein the at least one processor device uses a reclaim task to fill the build queue.

6. The system of claim 4 , wherein the at least one processor device maintains the plurality of demote scan tasks by adding or removing task control blocks (TCB) according to a number of allocation requests.

7. A computer program product for increased cache performance efficiency in a computing environment by a processor device, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising:
a first executable portion that distributes to each one of a plurality of central processing units (CPUs) workload operations for creating complete cache tracks from partial cache tracks by creating a complete cache track queue and a partial cache track pointer without a lock by each one of the CPUs;
a second executable portion that uses, by each one of the CPUs, an assembler queue to accumulate each of the complete cache tracks from the partial cache tracks including using a pointer copy of a partial cache track to assemble a complete cache track, the assembler queue sending each of the complete cache tracks to the complete cache track queue;
a third executable portion that creates sub-queues in front of each of the assembler queues accumulating the complete cache tracks, the sub-queues including both an append queue and a build queue, wherein the build queue fills the append queue using segments from the partial cache track pointer copy combined with a partial cache track and the append queue fills the assembler queue; and
a fourth executable portion that creates and throttles a plurality of demote scan tasks to continuously maintain pace with the filling of the complete cache track queue, the assembler queue, and the sub-queues.

8. The computer program product of claim 7 , further including a sixth executable portion that uses a reclaim task to fill the build queue.

9. The computer program product of claim 7 , further including a fifth executable portion that maintains the plurality of demote scan tasks by adding or removing task control blocks (TCB) according to a number of allocation requests.

Assignees

• IBM

Inventors

• Ash Kevin J
• Gupta Lokesh M
• Whitworth David B
• Zhao Boyan

Classifications

• G06F2212/45

  Caching of specific data in cache memory · CPC title

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F3/06

  Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers} · CPC title