Memory access control device, cache memory and semiconductor device

Patent metadata

Field	Value
Publication number	US-9684602-B2
Application number	US-201514931724-A
Country	US
Kind code	B2
Filing date	Nov 3, 2015
Priority date	Mar 11, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A memory access control device of an embodiment includes a data memory configured to record information of an access request relating to reading and writing of data to a main memory, and a controller configured to receive notification of the access request and select an access destination with reference to recording content of the data memory. When history of a request for write access and history of a request for read access to an address designated by the access request are recorded in the data memory, the controller selects a cache memory as the access destination, and otherwise, selects the main memory as the access destination.

First claim

What is claimed is:

1. A memory access control device comprising:
a data memory configured to record information of an access request relating to reading and writing of data to a main memory; and
a controller configured to receive the access request and select an access destination with reference to recording content of the data memory,
wherein when history of a request for write access and a request for read access to an address designated by the access request is recorded in the data memory, the controller selects a cache memory as the access destination, and otherwise, selects the main memory as the access destination.

2. The memory access control device according to claim 1 ,
wherein the data memory comprises:
a history buffer unit configured to record information of history of the request for write access; and
a cache tag unit configured to record a balance between the request for write access and the request for read access to a same address.

3. The memory access control device according to claim 2 ,
wherein the cache tag unit comprises a plurality of cache tag entries, and
each of the cache tag entries comprises:
a tag indicating an address of a storage destination of the data; and
a counter indicating a difference between a size of the data written and a size of the data read.

4. The memory access control device according to claim 3 ,
wherein, when the controller receives the request for read access, if a valid cache tag entry for a tag indicating a read address does not exist in the cache tag unit and there is an entry having a same tag as a tag indicating the read address in the history buffer unit, the controller notifies the cache tag unit of addition of the cache tag entry.

5. The memory access control device according to claim 3 ,
wherein, when the controller receives the request for read access, if the cache tag entry designated by the request for read access does not exist in the cache tag unit and all the cache tag entries are set valid, the controller makes the cache tag entry satisfying predetermined conditions invalid.

6. The memory access control device according to claim 5 ,
wherein the controller makes the cache tag entry having a value of the counter exceeding a first threshold invalid.

7. The memory access control device according to claim 5 ,
wherein the controller makes the cache tag entry having a value of the counter less than a second threshold invalid.

8. The memory access control device according to claim 5 ,
wherein the controller makes the cache tag entry which is not referred to for a longest time period invalid.

9. A cache memory comprising:
a memory configured to temporarily hold data and an address of the data; and
a memory access control device,
wherein the memory access control device comprises:
a data memory configured to record information of an access request relating to reading and writing of data to a main memory; and
a controller configured to receive the access request and select an access destination with reference to recording content of the data memory, and
when history of a request for write access and history of a request for read access to an address designated by the access request are recorded in the data memory, the controller selects the memory as the access destination, and otherwise, selects the main memory as the access destination.

10. The cache memory according to claim 9 ,
wherein the data memory comprises:
a history buffer unit configured to record the history of the request for write access; and
a cache tag unit configured to record a balance between the request for write access and the request for read access to a same address.

11. The cache memory according to claim 10 ,
wherein the cache tag unit comprises a plurality of cache tag entries, and
each of the cache tag entries comprises:
a tag indicating an address of a storage destination of the data; and
a counter indicating a difference between a size of the data written and a size of the data read.

12. The cache memory according to claim 11 ,
wherein when the controller receives the request for read access, if a valid cache tag entry for a tag indicating a read address does not exist in the cache tag unit and there is an entry having a same tag as a tag indicating the read address in the history buffer unit, the controller notifies the cache tag unit of addition of the cache tag entry.

13. The cache memory according to claim 11 ,
wherein when the controller receives the request for read access, if the cache tag entry designated by the request for read access does not exist in the cache tag unit and all the cache tag entries are set valid, the controller makes the cache tag entry satisfying predetermined conditions invalid.

14. The cache memory according to claim 13 ,
wherein the controller makes the cache tag entry having a value of the counter exceeding a first threshold invalid.

15. The cache memory according to claim 13 ,
wherein the controller makes the cache tag entry having a value of the counter less than a second threshold invalid.

16. The cache memory according to claim 13 ,
wherein the controller makes the cache tag entry which is not referred to for a longest time period invalid.

17. A semiconductor device comprising:
a processor;
a main memory;
a cache memory configured to temporarily store data to be stored in the main memory and an address; and
a memory access control device,
wherein the memory access control device comprises:
a data memory configured to record information of an access request relating to reading and writing of data to the main memory; and
a controller configured to receive notification of the access request and select an access destination with reference to recording content of the data memory,
wherein, when history of a request for write access and history of a request for read access to an address designated by the access request are recorded in the data memory, the controller selects the cache memory as the access destination, and otherwise, selects the main memory as the access destination.

18. The semiconductor device according to claim 17 ,
wherein the data memory comprises:
a history buffer unit configured to record the history of the request for write access; and
a cache tag unit configured to record a balance between the request for write access and the request for read access to a same address.

19. The semiconductor device according to claim 18 ,
wherein the cache tag unit comprises a plurality of cache tag entries, and
each of the cache tag entries comprises:
a tag indicating an address of a storage destination of the data; and
a counter indicating a difference between a size of the data written and a size of the data read.

20. The semiconductor device according to claim 19 ,
wherein, when the controller receives the request for read access, if a valid cache tag entry for a tag indicating a read address does not exist in the cache tag unit and there is an entry having a same tag as a tag indicating the read address in the history buffer unit, the controller notifies the cache tag unit of addition of the cache tag entry.

Assignees

• Toshiba Kk

Inventors

• Maeda Seiji

Classifications

• G06F12/0888 Primary

  using selective caching, e.g. bypass · CPC title

• G06F2212/45

  Caching of specific data in cache memory · CPC title

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/123

  with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list · CPC title