In-memory interconnect protocol configuration registers

Patent metadata

Field	Value
Publication number	US-9767028-B2
Application number	US-201514928981-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	Oct 30, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

First claim

What is claimed is:

1. A method comprising:
storing a plurality of interconnect protocol configuration registers in a main memory space of a first node;
caching the plurality interconnect protocol configuration registers in a cache of the first node;
accessing, by a host node, a first interconnect protocol configuration register of the first node;
calculating a latency of an access to the first interconnect protocol configuration register; and
storing an indicator that the first interconnect protocol configuration register is stored in a dedicated register of the first node responsive to determining the latency is less than a programmable threshold.

2. The method as recited in claim 1 , further comprising
caching the first interconnect protocol configuration register in a cache of the host node.

3. The method as recited in claim 1 , further comprising:
prefetching, by a host node, the first interconnect protocol configuration register of the plurality of interconnect protocol configuration registers during a boot sequence;
caching the first interconnect protocol configuration register in a cache of the host node; and
evicting the first interconnect protocol configuration register from the cache of the host node responsive to completing the boot sequence.

4. The method as recited in claim 1 , further comprising storing an indicator that the first interconnect protocol configuration register is stored in the main memory space of the first node responsive to determining the latency is greater than a programmable threshold.

5. The method as recited in claim 4 , further comprising:
caching the first interconnect protocol configuration register in the host node responsive to storing an indicator that the first interconnect protocol configuration register is stored in the main memory space of the first node; and
preventing the first interconnect protocol configuration register from being cached in the host node responsive to storing an indicator that the first interconnect protocol configuration register is stored in a dedicated register of the first node.

6. The method as recited in claim 1 , wherein the first node is a processing-in-memory (PIM) node.

7. A system comprising:
a first node; and
a host node coupled to the first node;
wherein the first node is configured to:
store a plurality of interconnect protocol configuration registers in a main memory space of a first node;
cache the plurality interconnect protocol configuration registers in a cache of the first node;
access a first interconnect protocol configuration register of the first node;
calculate a latency of an access to the first interconnect protocol configuration register; and
store an indicator that the first interconnect protocol configuration register is stored in a dedicated register of the first node responsive to determining the latency is less than a programmable threshold.

8. The system as recited in claim 7 , wherein the host node is configured to
cache the first interconnect protocol configuration register in a cache of the host node.

9. The system as recited in claim 7 , wherein the host node is configured to:
prefetch the first interconnect protocol configuration register of the plurality of interconnect protocol configuration registers during a boot sequence;
cache the first interconnect protocol configuration register in a cache of the host node; and
evict the first interconnect protocol configuration register from the cache of the host node responsive to completing the boot sequence.

10. The system as recited in claim 7 , wherein the host node is further configured to store an indicator that the first interconnect protocol configuration register is stored in the main memory space of the first node responsive to determining the latency is greater than a programmable threshold.

11. The system as recited in claim 10 , wherein the host node is further configured to:
cache the first interconnect protocol configuration register in a cache of the host node responsive to storing an indicator that the first interconnect protocol configuration register is stored in the main memory space of the first node; and
prevent the first interconnect protocol configuration register from being cached in the host node responsive to storing an indicator that the first interconnect protocol configuration register is stored in a dedicated register of the first node.

12. The system as recited in claim 7 , wherein the first node is a processing-in-memory (PIM) node.

13. A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable by a processor to:
store a plurality of interconnect protocol configuration registers in a main memory space of a first node;
cache the plurality interconnect protocol configuration registers in a cache of the first node;
access, by a host node, a first interconnect protocol configuration register of the first node;
calculate a latency of an access to the first interconnect protocol configuration register; and
store an indicator that the first interconnect protocol configuration register is stored in a dedicated register of the first node responsive to determining the latency is less than a programmable threshold.

14. The non-transitory computer readable storage medium as recited in claim 13 , wherein the program instructions are further executable by a processor to
cache the first interconnect protocol configuration register in a cache of the host node.

15. The non-transitory computer readable storage medium as recited in claim 13 , wherein the program instructions are further executable by a processor to:
prefetch, by a host node, the first interconnect protocol configuration register of the plurality of interconnect protocol configuration registers during a boot sequence;
cache the first interconnect protocol configuration register in a cache of the host node; and
evict the first interconnect protocol configuration register from the cache of the host node responsive to completing the boot sequence.

16. The non-transitory computer readable storage medium as recited in claim 13 , wherein the program instructions are further executable by a processor to store an indicator that the first interconnect protocol configuration register is stored in the main memory space of the first node responsive to determining the latency is greater than a programmable threshold.

17. The non-transitory computer readable storage medium as recited in claim 13 , wherein the program instructions are further executable by a processor to:
cache the first interconnect protocol configuration register in the host node responsive to storing an indicator that the first interconnect protocol configuration register is stored in the main memory space of the first node; and
prevent the first interconnect protocol configuration register from being cached in the host node responsive to storing an indicator that the first interconnect protocol configuration register is stored in a dedicated register of the first node.

18. A method comprising:
storing a plurality of interconnect protocol configuration registers in a main memory space of a first node;
caching the plurality interconnect protocol configuration registers in a cache of the first node;
prefetching, by a host node, a first interconnect protocol configuration register of the plurality of interconnect protocol configuration registers during a boot sequence;
caching the first interconnect protocol configuration register in a cache of the h

Assignees

• Advanced Micro Devices Inc

Inventors

• Cheng Kevin Y
• Roberts David A

Classifications

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F2212/45

  Caching of specific data in cache memory · CPC title

• G06F15/7821

  Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory · CPC title

• G06F2212/1024

  Latency reduction · CPC title