Distributed history buffer flush and restore handling in a parallel slice design

Patent metadata

Field	Value
Publication number	US-9740620-B2
Application number	US-201514706815-A
Country	US
Kind code	B2
Filing date	May 7, 2015
Priority date	May 7, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

An approach is provided in which a computing system captures content included in a history buffer entry that corresponds to a flush ITAG. The computing system, in turn, uses an execution unit to transmit the content over a results bus to multiple registers and restore at least one of the registers accordingly.

First claim

The invention claimed is:

1. An information handling system comprising:
one or more processors;
a memory coupled to at least one of the processors; and
a set of computer program instructions stored in the memory and executed by at least one of the processors in order to perform actions of:
sending recovery content included in a history buffer entry to an issue queue, wherein the history buffer entry corresponds to a flush instruction tag (ITAG), and wherein the recovery content comprises the history buffer entry in its entirety that includes register contents from a previous state;
passing the recovery content from the issue queue to an execution unit in response to the issue queue determining that the recovery content corresponds to a restore operation;
transmitting, by the execution unit included in the processor, the recovery content to a plurality of registers over a results bus; and
restoring at least one of the plurality of registers with the recovery content.

2. The information handling system of claim 1 wherein the history buffer entry is included in a history buffer.

3. The information handling system of claim 2 wherein the one or more processors perform additional actions comprising:
receiving, at the history buffer, results data corresponding to the flush ITAG subsequent to sending the recovery content to the issue queue and before a pre-determined restore delay period;
updating the recovery content to include the results data; and
transmitting the updated recovery content to the plurality of registers.

4. The information handling system of claim 1 further comprising:
a plurality of slices, each one of the plurality of slices comprising one of a plurality of history buffers, one of a plurality of issue queues, and one of a plurality of execution units; and
one or more super slices that each include the plurality of slices and one of the plurality of registers.

5. The information handling system of claim 4 wherein the one or more processors perform additional actions comprising:
transmitting the recovery content from the execution unit residing on a first one of the one or more super slices to the one of the plurality of registers that reside on a second one of the one or more super slices.

6. The information handling system of claim 1 wherein the one or more processors perform additional actions comprising:
identifying a first thread, from a plurality of threads, that corresponds to the flush ITAG; and
setting a recovery mask bit that corresponds to the first thread, wherein the recovery mask bit informs a dispatch unit included in the processor to discontinue dispatching instructions targeted to the first thread.

7. The information handling system of claim 6 wherein the one or more processors perform additional actions comprising:
dispatching an instruction corresponding to a second one of the plurality of threads while the dispatcher is discontinuing dispatching instructions targeted to the first thread.

8. A computer program product stored in a computer readable storage medium, comprising computer program code that, when executed by an information handling system, causes the information handling system to perform actions comprising:
sending recovery content included in a history buffer entry to an issue queue, wherein the history buffer entry corresponds to a flush instruction tag (ITAG), and wherein the recovery content comprises the history buffer entry in its entirety that includes register contents from a previous state;
passing the recovery content from the issue queue to an execution unit in response to the issue queue determining that the recovery content corresponds to a restore operation;
transmitting, by the execution unit included in the processor, the recovery content to a plurality of registers over a results bus; and
restoring at least one of the plurality of registers with the recovery content.

9. The computer program product of claim 8 wherein the history buffer entry is included in a history buffer.

10. The computer program product of claim 9 wherein the information handling system performs additional actions comprising:
receiving, at the history buffer, results data corresponding to the flush ITAG subsequent to sending the recovery content to the issue queue and before a pre-determined restore delay period;
updating the recovery content to include the results data; and
transmitting the updated recovery content to the plurality of registers.

11. The computer program product of claim 8 wherein the information handling system further comprises:
a plurality of slices, each one of the plurality of slices comprising one of a plurality of history buffers, one of a plurality of issue queues, and one of a plurality of execution units; and
one or more super slices that each include the plurality of slices and one of the plurality of registers.

12. The computer program product of claim 11 wherein the information handling system performs additional actions comprising:
transmitting the recovery content from the execution unit residing on a first one of the one or more super slices to the one of the plurality of registers that reside on a second one of the one or more super slices.

13. The computer program product of claim 8 wherein the information handling system performs additional actions comprising:
identifying a first thread, from a plurality of threads, that corresponds to the flush ITAG;
setting a recovery mask bit that corresponds to the first thread, wherein the recovery mask bit informs a dispatch unit included in the processor to discontinue dispatching instructions targeted to the first thread; and
dispatching an instruction corresponding to a second one of the plurality of threads while the dispatcher is discontinuing dispatching instructions targeted to the first thread.

Assignees

• IBM

Inventors

• Ayub Salma
• Chadha Sundeep
• Genden Michael J
• Kucharski Cliff
• Nguyen Dung Q
• Terry David R

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F9/3863 Primary

  using multiple copies of the architectural state, e.g. shadow registers · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F2212/60

  Details of cache memory · CPC title

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title