Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device

Patent metadata

Field	Value
Publication number	US-9747041-B2
Application number	US-201514757926-A
Country	US
Kind code	B2
Filing date	Dec 23, 2015
Priority date	Dec 23, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2 n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

First claim

What is claimed:

1. An apparatus, comprising:
a first level memory device having a non-power of 2 cache size to cache data present in a second level memory device having a 2 n size larger than the non-power of 2 cache size of the first level memory device; and
a cache manager to:
receive a request to a target address having n bits directed to the second level memory device;
determine whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device, wherein an index set of 2 m is greater in size than the index set in the first level memory device;
determine a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index; and
process the request with respect to data in a cache line at the modified target index in the first level memory device.

2. The apparatus of claim 1 , wherein the determining the modified target index comprises toggling the corresponding at least one index bit in the target index to produce the at least one index bit in the modified target index that differs from the corresponding at least one index bit in the target index.

3. The apparatus of claim 1 , wherein 2 m is equal to 2 k divided by a cache line size of cache lines in the first level memory device, where k comprises a lowest integer value such that 2 k is greater than the non-power of 2 cache size.

4. The apparatus of claim 1 , wherein the cache manager is further to:
save the corresponding at least one index bit from the target index that differs from the at least one index bit in the modified target index in a tag in the cache line at the modified target index in the first level memory device.

5. The apparatus of claim 4 , wherein the cache manager is further to:
in response to determining that the target index is within the index set of the first level memory device, save in the tag the at least one index bit in the target index that would have been changed if the target index was not in the index set of the first level memory device.

6. The apparatus of claim 4 , wherein the tag includes at least one of a most significant non-index bits of the target address and the at least one index bit in the target index that is modified if the target index is not within the index set of the first level memory device.

7. The apparatus of claim 6 , wherein the target address further includes b offset bits to address each of a 2 b data bytes in the cache line, wherein the tag includes (n-m-b) of the most significant non-index bits of the target address and the at least one most significant index bit in the target index that is modified if the target index is not within the index set of the first level memory device, wherein the tag includes the at least one most significant index bit when the target index is within and not within the index set of the first level memory device.

8. The apparatus of claim 4 , wherein the cache manager is further to:
form a formed tag for the target address comprising at least one most significant bit from the target index and at least one most significant bit of the target address following the target index;
determine whether the formed tag matches the tag in the cache line at the modified target index;
fetch data at the target address in the second level memory device to store in the cache line in response to determining that the formed tag not match the tag in the cache line; and
process the request in response to the fetching of the data.

9. The apparatus of claim 8 , wherein the cache manager is further to:
process the request with respect to the data in the cache line in response to determining that the formed target tag matches the tag in the cache line.

10. The apparatus of claim 1 , wherein the first level memory device comprises a volatile memory device and the second level memory device comprises a byte addressable non-volatile random access memory device.

11. A system, comprising:
a processor having a cache manager;
a main memory for the processor including a first level memory device and a second level memory device, wherein the first level memory device caches data for the second level memory device, and wherein the first level memory device has a non-power of 2 cache size to cache data present in the second level memory device having a 2 n size larger than the non-power of 2 cache size of the first level memory device; and
a cache manager to:
receive a request to a target address having n bits directed to the second level memory device;
determine whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device, wherein an index set of 2 m is greater in size than the index set in the first level memory device;
determine a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index; and
process the request with respect to data in a cache line at the modified target index in the first level memory device.

12. The system of claim 11 , wherein the determining the modified target index comprises toggling the corresponding at least one index bit in the target index to produce the at least one index bit in the modified target index that differs from the corresponding at least one index bit in the target index.

13. The system of claim 11 , wherein the cache manager is further configured to:
save the corresponding at least one index bit from the target index that differs from the at least one index bit in the modified target index in a tag in the cache line at the modified target index in the first level memory device.

14. The system of claim 13 , wherein the cache manager is further configured to:
in response to determining that the target index is within the index set of the first level memory device, save in the tag the at least one index bit in the target index that would have been changed if the target index was not in the index set of the first level memory device.

15. The system of claim 13 , wherein the tag includes at least one of a most significant non-index bits of the target address and the at least one index bit in the target index that is modified if the target index is not within the index set of the first level memory device.

16. The system of claim 15 , wherein the target address further includes b offset bits to address each of a 2 b data bytes in the cache line, wherein the tag includes (n-m-b) of the most significant non-index bits of the target address and the at least one most significant index bit in the target index that is modified if the target index is not within the index set of the first level memory device, wherein the tag includes the at least one most significant index bit when the target index is within and not within the index set of the first level memory device.

17. The system of claim 13 , wherein the cache manager is further configured to:
form a formed tag for the target address comprising at least one most significant bit from the target index and at least one most significant bit of the target address following the target index;
determine whether the formed tag matches the tag in the cache line at the modified target index;
fetch data at the target address in the second level memory device to store in the cache line in response to determining that the formed tag not match the tag in the cache line; and
process the request in re

Assignees

• Intel Corp

Inventors

• Geetha Vedaraman
• Neefs Henk G
• Morris Brian S
• Mandava Sreenivas
• Sutera Massimo

Classifications

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F2212/45

  Caching of specific data in cache memory · CPC title

• G06F3/068

  Hybrid storage device · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F3/0638

  Organizing or formatting or addressing of data · CPC title