Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods

Patent metadata

Field	Value
Publication number	US-9740621-B2
Application number	US-201514716108-A
Country	US
Kind code	B2
Filing date	May 19, 2015
Priority date	May 21, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods are disclosed. In certain aspects, memory controllers are employed that can provide memory capacity compression. In certain aspects disclosed herein, a next read address prefetching scheme can be used by a memory controller to speculatively prefetch data from system memory at another address beyond the currently accessed address. Thus, when memory data is addressed in the compressed memory, if the next read address is stored in metadata associated with the memory block at the accessed address, the memory data at the next read address can be prefetched by the memory controller to be available in case a subsequent read operation issued by a central processing unit (CPU) has been prefetched by the memory controller.

First claim

What is claimed is:

1. A memory controller, comprising:
a memory interface configured to access a system memory; and
a controller configured to:
receive a first memory read request comprising a first physical address (PA) to be read in the system memory over a system bus; and
access the first PA in the system memory to perform the received first memory read request; and

the controller further configured to:
receive a next memory read request comprising a next PA to be read in the system memory over the system bus;
access the system memory based on the next PA to perform the received next memory read request;
store the next PA in the system memory in association with the first PA; and
store the next PA in a cache entry associated with the first PA in a prefetch metadata (PMD) cache comprising a plurality of cache entries each comprising a first PA entry and a corresponding next PA entry, the PMD cache communicatively coupled to the memory controller.

2. The memory controller of claim 1 , wherein the controller is configured to store the next PA as metadata in a memory block associated with the first PA in the system memory.

3. The memory controller of claim 2 , wherein the controller is configured to:
determine if the memory block associated with the first PA contains available space to store the next PA; and
store the next PA as the metadata in the memory block associated with the first PA in the system memory, if the memory block associated with the first PA contains the available space for the next PA.

4. The memory controller of claim 3 , wherein the available space in the memory block associated with the first PA is based on a size of compressed memory data stored in the memory block.

5. The memory controller of claim 1 , wherein the controller is further configured to:
determine if a current PA for a received memory read request in contained in a repository in response to the controller performing a read operation for the current PA; and
if the next PA is stored in association with the current PA for the received memory read request in the repository:
read the next PA associated with the current PA in the system memory; and
prefetch memory data in the system memory at the next PA to obtain the memory data stored at the next PA as prefetched memory data.

6. The memory controller of claim 5 , wherein the controller is further configured to provide the prefetched memory data over the system bus.

7. The memory controller of claim 1 , wherein the controller is configured to store the next PA in the cache entry associated with the first PA in the PMD cache among a plurality of PMD caches each associated with a processor core, each of the plurality of PMD caches comprising the plurality of cache entries each comprising the first PA entry and the corresponding next PA entry, the PMD cache communicatively coupled to the memory controller.

8. The memory controller of claim 1 , wherein the controller is further configured to:
determine if a current PA for a received memory read request is contained in the PMD cache; and
if the current PA is contained in the PMD cache:
read the next PA associated with the current PA in the PMD cache in response to the controller performing a read operation for the current PA; and
prefetch memory data in the system memory at the next PA to obtain the memory data stored at the next PA as prefetched memory data.

9. The memory controller of claim 8 , wherein the controller is further configured to provide the prefetched memory data stored in the system memory at the next PA for the received memory read request over the system bus.

10. The memory controller of claim 8 , wherein, if the current PA for the received memory read request is not contained in the PMD cache, the controller is further configured to:
access the current PA in the system memory to obtain corresponding memory data stored in the current PA in the system memory; and
update the cache entry in the PMD cache corresponding to the current PA for the cache entry in the PMD cache in which the prefetched memory data was stored.

11. The memory controller of claim 10 , wherein the controller is further configured to:
determine if there is an available cache entry in the PMD cache; and
if there is not an available cache entry in the PMD cache, evict the cache entry in the PMD cache to store the current PA in the evicted cache entry in the PMD cache.

12. The memory controller of claim 8 , further comprising a data cache comprising a plurality of data cache entries each configured to store memory data in association with an address entry,
wherein the controller is further configured to:
determine if the current PA matches an address entry in a data cache entry among the plurality of data cache entries in the data cache; and
if the current PA is contained in the address entry in the data cache entry in the data cache, provide the corresponding memory data stored in the system memory at the current PA in the data cache as the prefetched memory data for the received memory read request.

13. The memory controller of claim 12 , wherein, if the current PA is contained in the address entry in the data cache entry in the data cache, the controller is further configured to:
read the next PA associated with the current PA in the PMD cache; and
prefetch memory data in the system memory at the next PA to obtain the memory data stored at the next PA as the prefetched memory data for the received memory read request.

14. The memory controller of claim 12 , wherein, if the current PA does not match the address entry in the data cache entry in the data cache, the controller is further configured to:
evict a data cache entry among the plurality of data cache entries in the data cache;
read the memory data from the system memory at the current PA and store the memory data in the data cache;
determine if the next PA is contained in the PMD cache; and
if the next PA is contained in the PMD cache, prefetch memory data from the system memory at the next PA as the prefetched memory data for the received memory read request.

15. The memory controller of claim 14 , wherein, if the current PA does not match the address entry in the data cache entry in the data cache, the controller is further configured to:
access the next PA associated with the current PA in the PMD cache;
write back the next PA in the system memory associated with the current PA if the evicted data cache entry is dirty; and
write back the next PA in the system memory associated with the current PA if the next PA associated with the current PA in the PMD cache is dirty with a configurable probability.

16. The memory controller of claim 13 , wherein, if the next PA is not contained in the PMD cache, the controller is further configured to:
read the next PA associated with the current PA in the system memory;
if the next PA associated with the current PA in the system memory is valid, prefetch the memory data from the system memory at the next PA as the prefetched memory data for the received memory read request; and
write back the next PA in the PMD cache in association with the current PA.

17. The memory controller of claim 12 , wherein the controller is further configured to:
receive a memory write request comprising a second PA and write memory data to be stored in the system memory over the system bus;
determine if the second PA matches an address entry in a data cache entry among the plurality of data cache entries in the data cache;
if the second PA is contained in the address entry in

Assignees

• Qualcomm Inc

Inventors

• Heddes Mattheus Cornelis Antonius Adrianus
• Vaidhyanathan Natarajan
• Verrilli Colin Beaton

Classifications

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• H03M7/30

  Compression (speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N); Expansion; Suppression of unnecessary data, e.g. redundancy reduction · CPC title

• G06F2212/401

  Compressed data · CPC title

• G06F2212/45

  Caching of specific data in cache memory · CPC title