Integrated circuit with multi-bit clock gating cells
US-9838013-B2 · Dec 5, 2017 · US
Clock gating
Clock gating · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F2117/04 |
| Official title | Clock gating |
| Display label | Clock gating |
| Total patents | 214 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 30 |
| 2016 | 17 |
| 2017 | 14 |
| 2018 | 22 |
| 2019 | 26 |
| 2020 | 21 |
| 2021 | 18 |
| 2022 | 19 |
| 2023 | 12 |
| 2024 | 18 |
| 2025 | 13 |
| 2026 | 4 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Glitch-aware phase algebra for clock analysis
US-9830412-B2 · Nov 28, 2017 · US
Level balanced clock tree
US-9823688-B2 · Nov 21, 2017 · US
Phase algebra for analysis of hierarchical designs
US-9798844-B2 · Oct 24, 2017 · US
Integrated circuit with multi-bit clock gating cells
US-2017302277-A1 · Oct 19, 2017 · US
Low power minimal disruptive method to implement large quantity push and pull useful-skew schedules with enabling circuits in a clock-mesh based design
US-9779201-B2 · Oct 3, 2017 · US
Method for finding non-essential flip flops in a VLSI design that do not require retention in standby mode
US-9727686-B2 · Aug 8, 2017 · US
Method for gating clock signals using late arriving enable signals
US-9672305-B1 · Jun 6, 2017 · US
Method and apparatus for performing logic synthesis
US-9652572-B2 · May 16, 2017 · US
Integrated circuit design method reducing clock power and integrated clock gater merged with flip-flops
US-2017061057-A1 · Mar 2, 2017 · US
Static checking of asynchronous clock domain crossings
US-9547732-B2 · Jan 17, 2017 · US
Methods for generating a contributor-based power abstract for a device
US-2017004234-A1 · Jan 5, 2017 · US
Methods for static checking of asynchronous clock domain crossings
US-9536024-B2 · Jan 3, 2017 · US
Semiconductor integrated circuit device
US-2016365358-A1 · Dec 15, 2016 · US
Power gating and clock gating in wiring levels
US-9520876-B1 · Dec 13, 2016 · US
Power savings method in a clock mesh-based design through a smart decloning technique
US-2016328507-A1 · Nov 10, 2016 · US
Level Balanced Clock Tree
US-2016299524-A1 · Oct 13, 2016 · US
Semiconductor integrated circuit device
US-9455699-B2 · Sep 27, 2016 · US
Fixing of semiconductor hold time
US-9430608-B2 · Aug 30, 2016 · US
Clock topology planning for reduced power consumption
US-9411912-B1 · Aug 9, 2016 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F2117/04?
- CPC G06F2117/04 is the Cooperative Patent Classification code for “Clock gating.”
- How many patents are filed under CPC G06F2117/04 (Clock gating)?
- Our database includes 214 publications tagged with this CPC code.
- Is patent activity under CPC G06F2117/04 growing?
- Publication counts under this code: 18 in 2024 vs 13 in 2025 (latest complete years).