Level Balanced Clock Tree

Patent metadata

Field	Value
Publication number	US-2016299524-A1
Application number	US-201514681599-A
Country	US
Kind code	A1
Filing date	Apr 8, 2015
Priority date	Apr 8, 2015
Publication date	Oct 13, 2016
Grant date	—

Abstract

A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of intermediate levels, and a leaf level that is coupled to a number of clocked circuits. Clock gating circuits are placed at the leaf level of the clock tree, and at least some of the intermediate levels. Processing the preliminary clock tree design includes ensuring that an equal number of clock gating circuits are coupled between each leaf level clock gating circuit and the root node. After processing the preliminary clock tree design, clock tree synthesis is performed by executing a clock tree synthesis tool on a computer system to generate a synthesized clock tree design.

First claim

What is claimed is:

1 . A method comprising:
processing a preliminary clock tree circuit design for an integrated circuit on a computer system, wherein the preliminary clock tree design includes a root node at which a generated clock is connected, a plurality of intermediate levels, and a leaf level from which the preliminary clock tree circuit design is connected to a plurality of clocked devices in the integrated circuit, wherein the leaf level includes a plurality of leaf level clock gating circuits and at least a portion of the plurality of intermediate levels include clock gating circuits, and wherein the processing comprises:
modifying the preliminary clock tree circuit design to ensure that each leaf level clock gating circuit has an equal number of the clock gating circuits between that leaf level clock gating circuit and the root node; and
subsequent to processing the preliminary clock tree design, performing clock tree synthesis of the preliminary clock tree by executing a clock tree synthesis tool on the computer system to generate a synthesized clock tree design.

2 . The method as recited in claim 1 , further comprising modifying the clock gating circuits in at least one of the intermediate levels and the leaf level to ensure that a fan-out of each of the clock gating circuit at a given level of the preliminary clock tree design is within a respective specified range.

3 . The method as recited in claim 2 , further comprising:
modifying the leaf level clock gating circuits such that each leaf level clock gating circuit is coupled to at least a first minimum number of clocked devices and no more than a first maximum number of clocked devices; and modifying clock gating circuits at each of the intermediate levels such that each clock gating circuit at a given one of the intermediate levels is coupled to at least a second minimum number of next level clock gating circuits and no more than a maximum number of next level clock gating circuits.

4 . The method as recited in claim 1 , further comprising modifying selected ones of the plurality of clock gating circuits to be always active during operation of the integrated circuit.

5 . The method as recited in claim 1 , further comprising inhibiting placement of inverters or buffers between any two clock gating circuits in a branch of the synthesized clock tree design.

6 . The method as recited in claim 1 , wherein performing clock tree synthesis comprises selecting the clock gating circuits from a plurality of standard cells such that each of the clock gating circuits at the leaf level are substantially identical to one another.

7 . The method as recited in claim 1 wherein performing clock tree synthesis comprises selecting the clock gating circuits from a plurality of standard cells such that each of the clock gating circuits at a given one of the plurality of intermediate levels is substantially identical to other ones of the clock gating circuits at the given one of the plurality of intermediate levels.

8 . A non-transitory computer readable medium having program instructions stored thereon that, if executed, cause a computer to:
process a preliminary clock tree circuit design for an integrated circuit on a computer system, wherein the preliminary clock tree design includes a root node at which a generated clock is connected, a plurality of intermediate levels, and a leaf level from which the preliminary clock tree circuit design is connected to a plurality of clocked devices in the integrated circuit, wherein the leaf level includes a plurality of leaf level clock gating circuits and at least a portion of the plurality of intermediate levels include clock gating circuits, and wherein the processing comprises:
modifying the preliminary clock tree circuit design to ensure that each leaf level clock gating circuit has an equal number of the clock gating circuits between that leaf level clock gating circuit and the root node; and
subsequent to processing the preliminary clock tree design, perform clock tree synthesis of the preliminary clock tree by causing the computer system to execute a clock tree synthesis tool to generate a synthesized clock tree design.

9 . The computer readable medium as recited in claim 8 , wherein the instructions stored on the computer readable medium include a first script that, when executed by the computer system, modify the clock gating circuits in at least one of the intermediate levels and the leaf level to ensure that a fan-out of each of the clock gating circuit at a given level of the preliminary clock tree design is within a respective specified range.

10 . The computer readable medium as recited in claim 9 , wherein executing the first script comprises:
modifying the leaf level clock gating circuits such that each leaf level clock gating circuit is coupled to at least a first minimum number of clocked devices and no more than a first maximum number of clocked devices; and modifying clock gating circuits at each of the intermediate levels such that each clock gating circuit at a given one of the intermediate levels is coupled to at least a second minimum number of next level clock gating circuits and no more than a maximum number of next level clock gating circuits.

11 . The computer readable medium as recited in claim 8 , wherein the instructions stored on the computer readable medium include instructions that, when executed by the computer system, modify selected ones of the plurality of clock gating circuits to be always active during operation of the integrated circuit.

12 . The computer readable medium as recited in claim 8 , wherein the instructions stored on the computer readable medium include instructions that, when executed by the computer system, inhibit placement of inverters or buffers between any two clock gating circuits in a branch of the synthesized clock tree design.

13 . The computer readable medium as recited in claim 8 , wherein the instructions stored on the computer readable medium include instructions that, when executed by the computer system, select, during performing of the clock tree synthesis, the clock gating circuits from a plurality of standard cells such that each of the clock gating circuits at the leaf level are substantially identical to one another.

14 . The computer readable medium as recited in claim 8 , wherein the instructions stored on the computer readable medium include instructions that, when executed by the computer system, select, during the clock tree synthesis, the clock gating circuits from a plurality of standard cells such that each of the clock gating circuits at a given one of the plurality of intermediate levels is substantially identical to other ones of the clock gating circuits at the given one of the plurality of intermediate levels.

15 . An integrated circuit comprising:
a clock generation circuit configured to generate a clock signal; a plurality of clocked circuits coupled to receive the clock signal; and a clock tree comprising a plurality of clock gating circuits including a root level clock gating circuit at a root level of the clock tree, a plurality of intermediate level clock gating circuits in a plurality of intermediate levels of the clock tree, and a plurality of leaf level clock gating circuits at a leaf level of the clock tree, wherein each of the plurality of clocked circuits is coupled to receive the clock signal from a correspondingly coupled one of the leaf level clock gating circuits; wherein the plurality of clock gating circuits is arranged such that each leaf level clock gating circuit has an equal number of the plur

Assignees

• Apple Inc

Inventors

• Rajagopal Karthik
• Thondugulam Narayanan V
• Sharma Rahul

Classifications

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F30/396

  Clock trees · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F17/505

  Physics · mapped topic

• G06F2117/04

  Clock gating · CPC title