Method and apparatus for performing logic synthesis

Patent metadata

Field	Value
Publication number	US-9652572-B2
Application number	US-201314758971-A
Country	US
Kind code	B2
Filing date	Jan 8, 2013
Priority date	Jan 8, 2013
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.

First claim

The invention claimed is:

1. A method of designing at least a part of an integrated circuit, IC, design, the method comprising:
identifying a first and at least one further module within the IC design that are mutually exclusive;
selecting at least one register within the first identified module and at least one register within the at least one further identified module to be shared;
merging the first and at least one further mutually exclusive modules such that a register is shared between the first and at least one further mutually exclusive modules for the registers selected to be shared;
generating, by a signal processing module arranged to perform logic synthesis, a merged gate level netlist for the first and at least one further mutually exclusive modules; and
outputting a merged gate level netlist to a subsequent design phase.

2. The method of claim 1 , wherein the method comprises selecting registers to be shared based at least partly on the registers comprising analogous clock signal requirements.

3. The method of claim 2 , wherein the method comprises selecting registers to be shared based at least partly on the registers being part of a common clock gating group.

4. The method of claim 1 , wherein the method comprises selecting registers to be shared based at least partly on layout considerations for the first and at least one further mutually exclusive modules.

5. The method of claim 1 , wherein merging the first and at least one further mutually exclusive modules comprises copying non-shared elements from each of the first and at least one further mutually exclusive modules.

6. The method of claim 5 , wherein merging the first and at least one further mutually exclusive modules comprises branching an output of the at least one register to respective non-shared elements of each of the first and at least one further mutually exclusive modules.

7. The method of claim 5 , wherein merging the first and at least one further mutually exclusive modules comprises routing inputs to the register through at least one multiplexing component.

8. The method of claim 7 , wherein the method comprises configuring control signals for the at least one multiplexing component to enable selection of individual module functionality.

9. The method of claim 1 , wherein merging the first and at least one further mutually exclusive modules is performed prior to insertion of clock gating.

10. The method of claim 1 , wherein the method further comprises performing logic equivalence comparison for each of the first and at least one further merged modules.

11. An integrated circuit device comprising a first and at least one further mutually exclusive modules, wherein the first and at least one further mutually exclusive modules share the register implemented in accordance with the method of claim 1 .

12. An apparatus comprising at least one signal processing module arranged to perform logic synthesis of at least a part of an integrated circuit, IC, design, the at least one signal processing module being arranged to:
identify a first and at least one further module within the IC design that are mutually exclusive;
select at least one register within the first identified module and at least one register within the at least one further identified module to be shared; and
merge the first and at least one further mutually exclusive modules such that a register is shared between the first and at least one further mutually exclusive modules for the registers selected to be shared.

13. A non-transitory readable storage medium computer program product having executable program code stored therein for performing logic synthesis of at least a part of an integrated circuit, IC, design, the program code operable for:
identifying a first and at least one further module within the IC design that are mutually exclusive;
selecting at least one register within the first identified module and at least one register within the at least one further identified module to be shared; and
merging the first and at least one further mutually exclusive modules such that a register is shared between the first and at least one further mutually exclusive modules for the registers selected to be shared.

Assignees

• Freescale Semiconductor Inc
• Priel Michael
• Babitsky Eliya
• Berkovitz Asher
• Nusimovich Vladimir
• Nxp Usa Inc

Inventors

• Priel Michael
• Babitsky Eliya
• Berkovitz Asher
• Nusimovich Vladimir

Classifications

• G06F30/30 Primary

  Circuit design · CPC title

• G06F17/5045

  Physics · mapped topic

• G06F17/505 Primary

  Physics · mapped topic

• G06F2117/04

  Clock gating · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title