Power gating and clock gating in wiring levels

Patent metadata

Field	Value
Publication number	US-9520876-B1
Application number	US-201615045753-A
Country	US
Kind code	B1
Filing date	Feb 17, 2016
Priority date	Feb 17, 2016
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A semiconductor comprising a front end of line portion including a logical processing unit (LPU) and a second LPU. The first LPU configured to perform a first operation and the second LPU configured to perform a second operation following the first operation. A back end of line portion including a plurality of wiring levels, and further including a power gate and a clock gate that are integrated into one or more wiring levels of the plurality of wiring levels. The power gate and clock gate are further electrically connected to the first LPU by an enable wire. The power gate and clock gate are electrically connected to a power grid and a clock net, respectively, by the enable wire, and the enable wire is further electrically connected to a latch of the second LPU. A signal wire is electrically connected to the first LPU and to the latch.

First claim

What is claimed is:

1. A semiconductor comprising:
a front end of line portion that includes a first logical processing unit (LPU) and a second LPU, the first LPU designed to perform a first operation and the second LPU designed to perform a second operation following the first operation;
a back end of line (BEOL) portion that includes a plurality of wiring levels, and further includes a power gate and a clock gate that are integrated into one or more wiring levels of the plurality of wiring levels, the power gate and the clock gate are further electrically connected to the first LPU by an enable wire, the power gate and the clock gate are electrically connected to a power grid and a clock net, respectively, by the enable wire, and the enable wire is further electrically connected to a latch of the second LPU; and
a signal wire is electrically connected to the first LPU, and is also electrically connected to the latch.

2. The semiconductor of claim 1 , wherein the power gate, clock gate, power grid, and clock net are integrated into a same wiring level of the one or more wiring levels.

3. The semiconductor of claim 1 , wherein the latch is configured to activate the second LPU in response to receiving an electrical signal from both the enable wire and the signal wire.

4. The semiconductor of claim 1 , wherein the power gate is integrated into an electrical via of the one or more wiring levels.

5. The semiconductor of claim 1 , wherein the clock gate is integrated into an electrical via of the one or more wiring levels.

6. The semiconductor of claim 1 , wherein the power grid is integrated into an electrical via of the one or more wiring levels.

7. The semiconductor of claim 1 , wherein the clock net is integrated into an electrical via of the one or more wiring levels.

8. The semiconductor of claim 1 , wherein the power gate is a thin film field effect transistor that is configured to transmit an electrical signal, in response to receiving an electrical signal exiting the clock net, that activates the power grid.

9. The semiconductor of claim 1 , wherein the clock gate is a thin film field effect transistor that is configured to transmit an electrical signal, in response to receiving an electrical signal exiting the power grid, that activates the clock net.

10. The semiconductor of claim 1 , wherein the one or more wiring levels that include the power gate and the clock gate are located vertically above the power grid and the clock net.

11. The semiconductor of claim 10 , wherein the power gate and the clock gate are integrated into a same wiring level of the one or more wiring levels.

12. The semiconductor of claim 10 , wherein the power gate and the clock gate are integrated into different wiring levels of the one or more wiring levels.

13. A semiconductor system comprising:
a first logical processing unit (LPU) integrated in a front end of line portion transmitting an electrical signal, in response to a first operation being performed be the first LPU, via an enable wire to a power gate and a clock gate, the power gate and the clock gate are integrated into one or more wiring levels of a plurality of wiring levels of a back end of line (BEOL) portion;
the power gate and the clock gate activating a power grid and a clock net, respectively;
the enable wire transmitting an electrical signal to a latch of a second LPU once the power grid and the clock net are activated;
a signal wire transmitting an electrical signal, in response to the first operation being performed, to the latch; and
the second LPU being activated to perform a second operation in response to the latch receiving the electrical signal from the signal wire and the enable wire.

14. The semiconductor system of claim 13 , wherein the latch is configured to activate the second LPU in response to receiving an electrical signal from both the enable wire and the signal wire.

15. The semiconductor system of claim 13 , wherein the power gate is a thin film field effect transistor that is configured to transmit an electrical signal, in response to receiving an electrical signal exiting the clock net, that activates the power grid.

16. The semiconductor system of claim 13 , wherein the clock gate is a thin film field effect transistor that is configured to transmit an electrical signal, in response to receiving an electrical signal exiting the power grid, that activates the clock net.

17. The semiconductor system of claim 13 , wherein the one or more wiring levels that include the power gate and the clock gate are located vertically above the power grid and the clock net.

18. The semiconductor system of claim 17 , wherein the power gate and the clock gate are integrated into a same wiring level of the one or more wiring levels.

19. The semiconductor system of claim 17 , wherein the power gate and the clock gate are integrated into different wiring levels of the one or more wiring levels.

Assignees

• IBM

Inventors

• Chadwick Nathaniel R
• Hassan Tassbieh
• Peterson Kirk D
• Sheets Ii John E
• Whiteside Christine E

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W70/095

  of vias therein · CPC title