Low power minimal disruptive method to implement large quantity push and pull useful-skew schedules with enabling circuits in a clock-mesh based design

Patent metadata

Field	Value
Publication number	US-9779201-B2
Application number	US-201514686749-A
Country	US
Kind code	B2
Filing date	Apr 14, 2015
Priority date	Oct 27, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

According to one general aspect, a method may include receiving a digital circuit model that includes models of a clock mesh and a plurality of logic circuits, each logic circuit associated with end-points of the logic circuit. The method may also include identifying a cluster of end-points, wherein the cluster is associated with a common version of the clock signal. The method may also include identifying an associated skew-schedule for each end-point. The method may include determining a timing slack and skew schedule for each end-point within the cluster. The method may include adjusting a clock-gater cell, based upon a common push/pull schedule associated with the cluster. The method may further include inserting, for at least one end-point of the cluster, a skew-buffer, wherein a variant of the skew-buffer for a respective end-point is based upon a difference between the end-point's skew schedule and the common push/pull schedule.

First claim

What is claimed is:

1. A method comprising:
receiving a digital circuit model comprising models of:
a clock mesh configured to provide a clock signal to a plurality of logic circuits, and
a plurality of logic circuits, each logic circuit at least in partially controlled by an application of the clock signal to one or more end-points of the logic circuit;

identifying a cluster of end-points, wherein the cluster is at least partially controlled by a common version of the clock signal and a common enable signal;
identifying an associated skew-schedule for each end-point;
determining a timing slack and skew schedule for each end-point within the cluster;
adjusting a clock-gater cell in the digital circuit model, wherein the clock-gater cell sets a common latency for the cluster and comprises a variant of the clock-gater cell based upon a common push/pull schedule associated with the cluster;
inserting, for at least one end-point of the cluster, a skew-buffer into the digital circuit model, wherein a variant of the skew-buffer for a respective end-point is based upon a difference between the skew schedule associated with the respective end-point and the common push/pull schedule associated with the cluster; and
further comprising determining the common push/pull schedule associated with the cluster, wherein determining the common push/pull schedule associated with the cluster comprises determining a greatest amount of a number of push/pull steps that can be added/removed from the cluster before an additional of increase in the number push/pull steps is counter-productive.

2. The method of claim 1 , wherein determining the common push/pull schedule associated with the cluster comprising:
determining which variant of the clock-gater cell that results in a greatest sum of all a cumulative useful skew schedule delay associated with the end-points of the cluster, minus a new cumulative negative slack introduced with the end-points of the cluster.

3. The method of claim 1 , wherein all variants of the clock-gater cell, for a given drive strength, include a first physical footprint; and
wherein all variants of the skew-buffer, for a given drive strength, include a second physical footprint.

4. The method of claim 1 , further comprising:
tuning the cluster for a low power mode by swapping a non-enable-delayed variant of the clock-gater cell with a enable-delayed variant of the clock-gater cell, and wherein the non-enable-delayed variant of the clock-gater cell and the enable-delayed variant of the clock-gater cell both include substantially a same clock latency and a same physical footprint.

5. The method of claim 1 , wherein inserting, for each end-point of the cluster, an individual skew-buffer comprises, if the digital model already includes an older skew-buffer associated with a respective end-point, replacing the older skew-buffer with the individual skew-buffer.

6. The method of claim 1 , wherein inserting, for each end-point of the cluster, an individual skew-buffer comprises, if the digital model already includes an older skew-buffer associated with a respective end-point and an amount of skew schedule associated with the individual skew-buffer is zero, removing the older skew-buffer, and not replacing the older skew-buffer with the individual skew-buffer.

7. The method of claim 1 , wherein adjusting the clock-gater cell in the digital circuit model comprises:
if a cluster is associated with enough positive timing slack, inserting a variant of the clock-gater cell into the digital circuit model, wherein the variant provides less clock latency than the common latency associated with the cluster and also, during operation, consumes less power than a variant that provides the common push/pull schedule associated with the cluster.

8. An apparatus comprising:
a digital circuit receiver configured to:
receive a digital circuit model that comprises models of:
a clock mesh configured to provide a clock signal to a plurality of logic circuits and a plurality of logic circuits, each logic circuit at least in partially controlled by an application of the clock signal to one or more end-points of the logic circuit,

identify a cluster of end-points, wherein the cluster is at least partially controlled by a common version of the clock signal and a common enable signal,
identify an associated skew schedule for each end-point, and
determine a timing slack and skew schedule for each end-point within the cluster;

a clock-gater adjuster configured to:
adjust a clock-gater cell into the digital circuit model, wherein the clock-gater cell sets a common latency for the cluster and comprises a variant of the clock-gater cell based upon a common push/pull schedule amount associated with the cluster, and
determine a greatest amount of a number of push/pull steps that can be added/removed from the cluster before an additional of increase in the number push/pull steps is counter-productive; and

a skew buffer adjuster configured to insert, for at least one end-point of the cluster, a skew-buffer into the digital circuit model, wherein a variant of the skew-buffer for a respective end-point is based upon a difference between a skew schedule associated with the respective end-point and the common push/pull schedule amount associated with the cluster.

9. The apparatus of claim 8 , wherein the clock-gater adjuster is configured to set the common push/pull schedule amount associated with the cluster.

10. The apparatus of claim 9 , wherein the clock-gater adjuster is configured to determine which variant of the clock-gater cell that results in a greatest sum of all a cumulative useful skew schedule delay associated with the end-points of the cluster, minus a cumulative negative slacks introduced with the end-points of the cluster.

11. The apparatus of claim 8 , wherein all variants of the clock-gater cell, for a given drive strength, include a first physical footprint; and
wherein all variants of the skew-buffer, for a given drive strength, include a second physical footprint.

12. The apparatus of claim 8 , further comprising:
a low power tuner configured to tune the cluster for a low power mode by swapping a normal-power variant of the clock-gater cell with a enable-delayed variant of the clock-gater cell, and wherein the normal-power variant of the clock-gater cell and the enable-delayed variant of the clock-gater cell both include substantially a same clock latency and a same physical footprint.

13. The apparatus of claim 8 , wherein the clock-gater adjuster is configured to, if the digital model already comprises an older clock-gater cell associated with a respective cluster, replacing the older clock-gater cell with a new clock-gater cell.

14. The apparatus of claim 8 , wherein the skew buffer adjuster is configured to, if the digital model already comprises an older skew-buffer associated with a respective end-point and an amount of skew schedule associated with a new skew-buffer is zero, removing the older skew-buffer, and not replacing the older skew-buffer with the new skew-buffer.

15. The apparatus of claim 8 , wherein the digital circuit model comprises physical layout information; and
wherein the apparatus is configured to adjust the clock-gater cells and skew-buffers without causing the physical layout information of the digital circuit model to be invalid.

16. A computer program product for altering a clock skew schedule of a digital circuit model, the computer program product being tangibly embodied on a computer-readable medium and comprising executable code that, when executed, is conf

Assignees

• Millar Brian
• Chowdhury Ahsan
• Ahmed Suhail
• Berzins Matthew
• Lee Jinkyu
• Samsung Electronics Co Ltd

Inventors

• Millar Brian
• Chowdhury Ahsan
• Ahmed Suhail
• Berzins Matthew
• Lee Jinkyu

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/396

  Clock trees · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F17/5081 Primary

  Physics · mapped topic