Fixing of semiconductor hold time

Patent metadata

Field	Value
Publication number	US-9430608-B2
Application number	US-201514922275-A
Country	US
Kind code	B2
Filing date	Oct 26, 2015
Priority date	Dec 7, 2012
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with hold-time violations are wired later, thus fixing hold-time violations without scaling or adding further buffers. Hold times are re-evaluated once wiring of track routes is complete.

First claim

What is claimed is:

1. A computer-implemented method for design analysis and modification comprising:
estimating hold-time requirements for a semiconductor design based on ideal clocks;
allocating, using one or more processors, placement regions for the design wherein the placement regions are to be used during hold-time fixing, wherein the allocating of placement regions to be used during hold-time fixing allows for access to pins on blocks within the design;
wiring track routes for the design wherein the wiring of track routes for hold-time critical nets is performed later than wiring of nets without hold-time violations; and
modifying the design by performing hold-time fixing on the design.

2. The method of claim 1 wherein clock constraints are used as part of the estimating of hold-time requirements.

3. The method of claim 1 further comprising performing placement.

4. The method of claim 3 wherein the placement includes incremental global placement.

5. The method of claim 3 wherein the placement is based on buffers that are inserted as part of the hold-time fixing.

6. The method of claim 1 further comprising estimating a number of buffers required.

7. The method of claim 6 further comprising reserving required routing resources for the number of buffers.

8. The method of claim 1 further comprising placing buffers as part of the hold-time fixing.

9. The method of claim 8 wherein the hold-time fixing is performed before the placing of buffers.

10. The method of claim 1 further comprising determining critical clock-gate enable paths.

11. The method of claim 10 wherein the determining of the critical clock-gate enable paths is used in the hold-time fixing.

12. The method of claim 1 further comprising reordering scan chains after the hold-time fixing.

13. The method of claim 1 further comprising wiring track routes for the design wherein the wiring of track routes for hold-time critical nets is performed later than wiring of nets without hold-time violations.

14. The method of claim 1 further comprising re-evaluating hold times once the wiring of track routes is accomplished.

15. The method of claim 14 further comprising incrementally adjusting buffering to improve hold times.

16. The method of claim 1 wherein the performing of hold-time fixing avoids displacement of previously placed blocks.

17. The method of claim 1 further comprising performing clock-tree synthesis for the design.

18. The method of claim 17 further comprising incrementally removing space remaining in the placement regions that were allocated.

19. The method of claim 1 wherein the allocating of placement regions is based on estimates of needed buffers.

20. The method of claim 1 wherein the performing hold-time fixing includes ordering of net routing such that nets with hold-time violations are wired later in time.

21. A computer program product embodied in a non-transitory computer readable medium, which when executed by a processor, causes the processor to perform design analysis and modification, the computer program product comprising instructions that when executed cause the processor to:
estimate hold-time requirements for a semiconductor design based on ideal clocks;
allocate placement regions for the design wherein the placement regions are to be used during hold-time fixing, wherein the allocating of placement regions to be used during hold-time fixing allows for access to pins on blocks within the design;
wire track routes for the design wherein the wiring of track routes for hold-time critical nets is performed later than wiring of nets without hold-time violations; and
modify the design by performing hold-time fixing on the design.

22. The computer program product of claim 21 that further causes the processor to perform placement where the placement is based on buffers that are inserted as part of the hold-time fixing.

23. The computer program product of claim 21 that further causes the processor to estimate a number of buffers required and code for reserving required routing resources for the number of buffers.

24. The computer program product of claim 21 that further causes the processor to re-evaluate hold times once the wiring of track routes is accomplished.

25. The computer program product of claim 21 wherein the hold-time fixing on the design uses hold-fixing scenarios which are determined and activated prior to placement.

26. A computer system for design analysis and modification comprising:
a memory which stores instructions;
one or more processors coupled to the memory wherein the one or more processors are configured to:
estimate hold-time requirements for a semiconductor design based on ideal clocks;
allocate placement regions for the design wherein the placement regions are to be used during hold-time fixing, wherein the allocating of placement regions to be used during hold-time fixing allows for access to pins on blocks within the design;
wire track routes for the design wherein the wiring of track routes for hold-time critical nets is performed later than wiring of nets without hold-time violations; and
modify the design by performing hold-time fixing on the design.

27. The system of claim 26 wherein the wherein the one or more processors are further configured to perform placement where the placement is based on buffers that are inserted as part of the hold-time fixing.

28. The system of claim 26 wherein the wherein the one or more processors are further configured to estimate a number of buffers required and reserve required routing resources for the number of buffers.

29. The system of claim 26 wherein the wherein the one or more processors are further configured to wire track routes for the design and re-evaluate hold times once wiring of track routes is accomplished.

30. The system of claim 26 wherein the hold-time fixing on the design uses hold-fixing scenarios which are determined and activated prior to placement.

Assignees

• Synopsys Inc

Inventors

• Kalpat Karthik Ramaseshan
• Kumar Rohit
• Nimmagadda Narendra
• Shah Saumil Sanjay
• Tseng Hsiao-Ping

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5081 Primary

  Physics · mapped topic

• G06F17/5077

  Physics · mapped topic