Semiconductor integrated circuit device

Patent metadata

Field	Value
Publication number	US-9455699-B2
Application number	US-201514746920-A
Country	US
Kind code	B2
Filing date	Jun 23, 2015
Priority date	Jun 7, 2005
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

First claim

What is claimed is:

1. A semiconductor integrated circuit device formed on one chip comprising:
a first functional block connected to a first power supply line and a second power supply line;
a second functional block connected to the first power supply line and a third power supply line and communicating with the first functional block;
a third functional block connected to the first power supply line and a fourth power supply line and communicating with the first functional block;
a first power switch shutting down the first functional block from power supply via the second power supply line;
a second power switch shutting down the second functional block from power supply via the third power supply line; and
a third power switch shutting down the third functional block from power supply via the fourth power supply line,
wherein the first functional block is shut down by the first switch when the second and the third functional blocks are shut down,
wherein the first functional block includes a first well of a first conduction type,
wherein the second functional block includes a second well of the first conduction type,
wherein a third well of a second conduction type separates the first well and the second well.

2. A semiconductor integrated circuit device according to claim 1 ,
wherein the first conduction type is N-type and the second conduction type is P-type.

3. A semiconductor integrated circuit device according to claim 2 ,
wherein a first voltage is supplied to the first power supply line and a second voltage is supplied to the second and the fourth power supply lines.

4. A semiconductor integrated circuit device according to claim 3 ,
wherein the first voltage is higher than the second voltage.

5. A semiconductor integrated circuit device according to claim 1 ,
wherein a signal transmission between the second functional block and the third functional block is performed via the first functional block.

6. A semiconductor integrated circuit device according to claim 5 ,
wherein the signal transmission between the second functional block and the third functional block is performed via a signal relay buffer circuit provided in the first functional block.

7. A semiconductor integrated circuit device according to claim 6 ,
wherein the first functional block comprises a retaining latch circuit that saves a data from one of the second and third functional blocks.

Assignees

• Renesas Electronics Corp

Inventors

• Kanno Yusuke
• Mizuno Hiroyuki
• Yasu Yoshihiko
• Hirose Kenji
• Irita Takahiro

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H03K3/0375

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title