Multibody simulation
US-2024169124-A1 · May 23, 2024 · US
Structured ASICs
Structured ASICs · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F2115/06 |
| Official title | Structured ASICs |
| Display label | Structured ASICs |
| Total patents | 235 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 12 |
| 2016 | 11 |
| 2017 | 13 |
| 2018 | 11 |
| 2019 | 27 |
| 2020 | 21 |
| 2021 | 23 |
| 2022 | 29 |
| 2023 | 30 |
| 2024 | 34 |
| 2025 | 21 |
| 2026 | 3 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Merged pillar structures and method of generating layout diagram of same
US-10515178-B2 · Dec 24, 2019 · US
Tapped inductor voltage controlled oscillator
US-2019372523-A1 · Dec 5, 2019 · US
Systems and methods for top level integrated circuit design
US-10474778-B2 · Nov 12, 2019 · US
Method and apparatus for performing register retiming by utilizing native timing-driven constraints
US-10417374-B1 · Sep 17, 2019 · US
Tapped inductor voltage controlled oscillator
US-10411647-B2 · Sep 10, 2019 · US
Integrated circuit layout, structure, system, and methods
US-2019251223-A1 · Aug 15, 2019 · US
Effective substitution of global distributed head switch cells with cluster head switch cells
US-10346574-B2 · Jul 9, 2019 · US
System and method for assigning color pattern
US-10318698-B2 · Jun 11, 2019 · US
Hybrid timing analysis method and associated system and non-transitory computer readable medium
US-10268787-B2 · Apr 23, 2019 · US
Merged pillar structures and method of generating layout diagram of same
US-2019065653-A1 · Feb 28, 2019 · US
Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework
US-10197908-B2 · Feb 5, 2019 · US
Methods and apparatus for performing timing driven hardware emulation
US-2019005174-A1 · Jan 3, 2019 · US
Method and apparatus for improving a design for a system during compilation by performing network replacement
US-10162919-B1 · Dec 25, 2018 · US
Effective substitution of global distributed head switch cells with cluster head switch cells
US-2018366367-A1 · Dec 20, 2018 · US
Architecture generating device
US-2018196907-A1 · Jul 12, 2018 · US
System and method for assigning color pattern
US-2018165406-A1 · Jun 14, 2018 · US
Methods and systems to estimate power network noise
US-2018165407-A1 · Jun 14, 2018 · US
Integrated circuit, system for and method of forming an integrated circuit
US-2018151411-A1 · May 31, 2018 · US
Method and circuit for via pillar optimization
US-9977857-B1 · May 22, 2018 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F2115/06?
- CPC G06F2115/06 is the Cooperative Patent Classification code for “Structured ASICs.”
- How many patents are filed under CPC G06F2115/06 (Structured ASICs)?
- Our database includes 235 publications tagged with this CPC code.
- Is patent activity under CPC G06F2115/06 growing?
- Publication counts under this code: 34 in 2024 vs 21 in 2025 (latest complete years).