Through-substrate via power gating and delivery bipolar transistor
US-10170578-B2 · Jan 1, 2019 · US
Effective substitution of global distributed head switch cells with cluster head switch cells
US10346574B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10346574-B2 |
| Application number | US-201715625754-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 16, 2017 |
| Priority date | Jun 16, 2017 |
| Publication date | Jul 9, 2019 |
| Grant date | Jul 9, 2019 |
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- Title
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- Abstract
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- First independent claim
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Abstract
Official abstract text for this publication.
An IC includes a first IC portion and a second IC portion. The IC includes a first set of standard cells in the first IC portion. The IC includes a plurality of memory cells and a second set of standard cells in the second IC portion. The second set of standard cells is located in channels between the memory cells. The IC further includes a plurality of GDHS cells in the first IC portion. The GDHS cells are configured to switch power on and to switch power off to the first set of standard cells. The IC further includes a plurality of CHS cells in the first IC portion. The CHS cells are configured to switch power on and to switch power off to the second set of standard cells in the second IC portion.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit (IC) including a first IC portion and a second IC portion, comprising: a first set of logic cells in the first IC portion; a plurality of memory cells and a second set of logic cells in the second IC portion, the second set of logic cells being located in channels between the memory cells; a plurality of global distributed head switch (GDHS) cells in the first IC portion, the GDHS cells being configured to switch power on and to switch power off to the first set of logic cells; and a plurality of cluster head switch (CHS) cells in the first IC portion, the CHS cells being configured to switch power on and to switch power off to the second set of logic cells in the second IC portion. 2. The IC of claim 1 , wherein the CHS cells are located on edges of the first IC portion adjacent the second IC portion. 3. The IC of claim 1 , further comprising: a power distribution network extending across the IC; and a redistribution layer (RDL) above the power distribution network, wherein the GDHS cells and the CHS cells are located below the power distribution network and are coupled to the power distribution network, and wherein the CHS cells are coupled to the second set of logic cells through the RDL. 4. The IC of claim 1 , wherein the first IC portion excludes memory cells. 5. A method of power gating of an integrated circuit (IC) including a first IC portion and a second IC portion, comprising: power gating a first set of logic cells in the first IC portion through a plurality of global distributed head switch (GDHS) cells in the first IC portion, the GDHS cells being configured to switch power on and to switch power off to the first set of logic cells; and power gating a second set of logic cells in the second IC portion through a plurality of cluster head switch (CHS) cells in the first IC portion, the second set of logic cells being located in channels between a plurality of memory cells in the second IC portion, the CHS cells being configured to switch power on and to switch power off to the second set of logic cells in the second IC portion. 6. The method of claim 5 , wherein the CHS cells are located on edges of the first IC portion adjacent the second IC portion. 7. The method of claim 5 , wherein the IC comprises: a power distribution network extending across the IC; and a redistribution layer (RDL) above the power distribution network, wherein the GDHS cells and the CHS cells are located below the power distribution network and are coupled to the power distribution network, and wherein the CHS cells are coupled to the second set of logic cells through the RDL. 8. The method of claim 5 , wherein the first IC portion excludes memory cells. 9. An apparatus for power gating of an integrated circuit (IC) including a first IC portion and a second IC portion, comprising: means for power gating a first set of logic cells in the first IC portion through a plurality of global distributed head switch (GDHS) cells in the first IC portion, the GDHS cells being configured to switch power on and to switch power off to the first set of logic cells; and means for power gating a second set of logic cells in the second IC portion through a plurality of cluster head switch (CHS) cells in the first IC portion, the second set of logic cells being located in channels between a plurality of memory cells in the second IC portion, the CHS cells being configured to switch power on and to switch power off to the second set of logic cells in the second IC portion. 10. The apparatus of claim 9 , wherein the CHS cells are located on edges of the first IC portion adjacent the second IC portion. 11. The apparatus of claim 9 , wherein the IC comprises: a power distribution network extending across the IC; and a redistribution layer (RDL) above the power distribution network, wherein the GDHS cells and the CHS cells are located below the power distribution network and are coupled to the power distribution network, and wherein the CHS cells are coupled to the second set of logic cells through the RDL. 12. The apparatus of claim 9 , wherein the first IC portion excludes memory cells.
Assignees
Inventors
Classifications
Manufacture or treatment · CPC title
Structured ASICs · CPC title
Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title
Physics · mapped topic
Electricity · mapped topic
Patent family
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US10346574B2 cover?
- An IC includes a first IC portion and a second IC portion. The IC includes a first set of standard cells in the first IC portion. The IC includes a plurality of memory cells and a second set of standard cells in the second IC portion. The second set of standard cells is located in channels between the memory cells. The IC further includes a plurality of GDHS cells in the first IC portion. The G…
- Who is the assignee on this patent?
- Qualcomm Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F17/5072. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jul 09 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).