Tapped inductor voltage controlled oscillator

Patent metadata

Field	Value
Publication number	US-10411647-B2
Application number	US-201715725964-A
Country	US
Kind code	B2
Filing date	Oct 5, 2017
Priority date	Mar 16, 2015
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A voltage controlled oscillator includes a resonator and an amplifier. The resonator includes a capacitive element and an inductive element. The inductive element has a plurality of conductive segments forming a physical loop. The inductive element has electrical connections on the physical loop to the plurality of conductive segments forming at least one electrical loop disposed within an interior space formed by the physical loop. The amplifier has an input and an output, the input coupled to a first conductive segment forming a first impedance and the output coupled to a second conductive segment forming a second impedance.

First claim

What is claimed is:

1. A differential tapped inductor comprising:
an inductive element with two differential inputs, the inductive element comprising a plurality of conductive segments forming a physical loop defining an interior, the inductive element tapped with a first electrical connection at a first point on the physical loop, the inductive element tapped with a second electrical connection at a second point on the physical loop, the plurality of conductive segments being made of a first thickness of a metal, the first electrical connection being made of a second thickness of the metal, the second thickness of the metal being less than the first thickness of the metal.

2. The differential tapped inductor of claim 1 , wherein the first electrical connection forms an electrical loop within the interior.

3. The differential tapped inductor of claim 2 , wherein the second electrical connection forms a second electrical loop within the interior.

4. The differential tapped inductor of claim 1 , wherein a parasitic resistance of the first electrical connection is higher than a parasitic resistance of the inductive element.

5. The differential tapped inductor of claim 1 , wherein the first electrical connection and the second electrical connection are centrally routed out of the interior.

6. The differential tapped inductor of claim 1 , wherein the physical loop is symmetrically shaped.

7. The differential tapped inductor of claim 1 , wherein the physical loop comprises a hexagonal shape.

8. A differential tank circuit resonator comprising:
a differential tapped inductor comprising:
an inductive element with two differential inputs, the inductive element comprising a plurality of conductive segments forming a physical loop defining an interior, the inductive element tapped with a first electrical connection at a first point on the physical loop, the inductive element tapped with a second electrical connection at a second point on the physical loop, the plurality of conductive segments being made of a first thickness of a metal, the first electrical connection being made of a second thickness of the metal, the second thickness of the metal being less than the first thickness of the metal; and
a capacitive element that connects the two differential inputs.

9. The differential tank circuit resonator of claim 8 , wherein the first electrical connection forms an electrical loop within the interior.

10. The differential tank circuit resonator of claim 9 , wherein the second electrical connection forms a second electrical loop within the interior.

11. The differential tank circuit resonator of claim 8 , wherein a parasitic resistance of the first electrical connection is higher than a parasitic resistance of the inductive element.

12. The differential tank circuit resonator of claim 8 , wherein the first electrical connection and the second electrical connection are centrally routed out of the interior.

13. The differential tank circuit resonator of claim 8 , wherein the physical loop is symmetrically shaped.

14. The differential tank circuit resonator of claim 8 , wherein physical loop comprises a hexagonal shape.

15. A computer-implemented method for manufacturing a differential tapped inductor, the method comprising:
generating a layout of a differential tapped inductor;
generating a photomask of the differential tapped inductor based on the layout; and
generating the differential tapped inductor in semiconductor material, based on the photomask, by:
forming an inductive element with two differential inputs, the inductive element comprising a plurality of conductive segments forming a physical loop defining an interior, the inductive element tapped with a first electrical connection at a first point on the physical loop, the inductive element tapped with a second electrical connection at a second point on the physical loop, the plurality of conductive segments being formed of a first thickness of a metal, the first electrical connection being formed of a second thickness of the metal, the second thickness of the metal being less than the first thickness of the metal.

16. The method of claim 15 , wherein the forming of the first electrical connection comprises forming an electrical loop within the interior.

17. The method of claim 16 , wherein the forming of the second electrical connection comprises forming a second electrical loop within the interior.

18. The method of claim 15 , wherein the forming of the first electrical connection forms the first electrical connection with a first parasitic resistance and forms the inductive element with a second parasitic resistance that is lower than the first parasitic resistance.

19. The method of claim 15 , wherein the forming of the first electrical connection and the second electrical connection comprises forming the first electrical connection and the second electrical connection centrally out of the interior.

20. The method of claim 15 , wherein the physical loop is symmetrically shaped.

Assignees

• Futurewei Technologies Inc

Inventors

• Bushman Michael L
• Duey Charles J
• Caldwell James W

Classifications

• G06F2115/06

  Structured ASICs · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H03B2200/004

  including a variable capacitance, e.g. a varicap, a varactor or a variable capacitance of a diode or transistor · CPC title

• H03B5/1206

  using multiple transistors for amplification · CPC title

• H03B2200/0012

  Pierce oscillator · CPC title