System and method for assigning color pattern

Patent metadata

Field	Value
Publication number	US-10318698-B2
Application number	US-201715595863-A
Country	US
Kind code	B2
Filing date	May 15, 2017
Priority date	Dec 14, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A method includes operations below. A layout of a circuit is converted to a first conflict graph. A first vertex and a second vertex in the first conflict graph are adjusted based on first data indicating a color patterns assignment for the circuit, in order to generate a second conflict graph, in which the first vertex indicates a first pattern in the layout, and the second vertex indicates a second pattern in the layout. According to the second conflict graph, a first color pattern is assigned to both of the first pattern and the second pattern, or the first color pattern is assigned to the first pattern and a second color pattern is assigned to the second pattern, in order to generate second data for fabricating the circuit.

First claim

What is claimed is:

1. A method, comprising:
converting, by a processor, a layout of a circuit to a first conflict graph;
adjusting, by the processor, a first vertex and a second vertex in the first conflict graph based on a first data indicating a color patterns assignment for the circuit, in order to generate a second conflict graph, wherein in the second conflict graph, the first vertex and the second vertex are adjusted to be a single vertex, or to be coupled to each other directly or via at least one pseudo vertex, the first vertex indicates a first pattern in the layout, the second vertex indicates a second pattern in the layout, and the at least one pseudo vertex indicates that no physical pattern corresponding to the at least one pseudo vertex is present in the layout; and
assigning, by the processor, according to the second conflict graph, a first color pattern to both of the first pattern and the second pattern, or the first color pattern to the first pattern and a second color pattern to the second pattern, in order to generate a second data; and
forming, by at least one manufacturing tool, the circuit based on the second data.

2. The method of claim 1 , wherein adjusting the first vertex and the second vertex comprises:
on condition that the first color pattern is determined, based on the first data, to be assigned to both of the first pattern and the second pattern, merging the first vertex and the second vertex as the single vertex to generate the second conflict graph.

3. The method of claim 1 , wherein adjusting the first vertex and the second vertex comprises:
on condition that the first color pattern is determined, based on the first data, to be assigned to both of the first pattern and the second pattern, adding the at least one pseudo vertex between the first vertex and the second vertex, wherein a number of the at least one pseudo vertex is one; and
coupling the first vertex to the second vertex via the at least one pseudo vertex, in order to generate the second conflict graph.

4. The method of claim 1 , wherein the at least one pseudo vertex has an odd number of pseudo vertices, and adjusting the first vertex and the second vertex comprises:
on condition that the first color pattern is determined, based on the first data, to be assigned to both of the first pattern and the second pattern, adding the odd number of pseudo vertices between the first vertex and the second vertex; and
coupling the first vertex to the second vertex via the odd number of pseudo vertices, in order to generate the second conflict graph.

5. The method of claim 1 , wherein adjusting the first vertex and the second vertex comprises:
on condition that the first color pattern is determined, based on the first data, to be assigned to the first pattern and the second color pattern is assigned to the second pattern, coupling the first vertex to the second vertex, in order to generate the second conflict graph.

6. The method of claim 5 , wherein the first vertex and the second vertex are directly coupled with each other.

7. The method of claim 1 , wherein the at least one pseudo vertex has an even number of pseudo vertices, and adjusting the first vertex and the second vertex comprises:
on condition that the first color pattern is determined, based on the first data, to be assigned to the first pattern and the second color pattern is assigned to the second pattern, adding the even number of pseudo vertices between the first vertex and the second vertex; and
coupling the first vertex to the second vertex via the even number of pseudo vertices, in order to generate the second conflict graph.

8. A system, comprising:
a memory configured to store computer program codes;
a processor configured to execute the computer program codes in the memory to:
adjust a first vertex and a second vertex in a plurality of vertices in a first conflict graph based on a first data indicating a color patterns assignment associated with the plurality of vertices, in order to generate a second conflict graph, wherein in the second conflict graph, the first vertex and the second vertex are adjusted to be a single vertex, or to be coupled to each other directly or via at least one pseudo vertex, and the at least one pseudo vertex indicates no physical pattern corresponding to the at least one pseudo vertex is present in a layout of a circuit; and
assign, according to the second conflict graph, the same color pattern or different color patterns to patterns, which correspond to the plurality of vertices, in the circuit, in order to generate a second data; and

at least one manufacturing tool configured to form the circuit based on the second data.

9. The system of claim 8 , wherein the processor is further configured to execute the computer program codes in the memory to:
convert the layout of the circuit to the first conflict graph.

10. The system of claim 8 , wherein on condition that the patterns corresponding to the plurality of vertices are determined to be assigned with the same color pattern, the processor is further configured to execute the computer program codes in the memory to:
merge the plurality of vertices as the single vertex to generate the second conflict graph.

11. The system of claim 8 , wherein on condition that the patterns corresponding to the plurality of vertices are determined to be assigned with the same color pattern, the processor is further configured to execute the computer program codes in the memory to:
add the at least one pseudo vertex between the plurality of vertices, wherein a number of the at least one pseudo vertex is one; and
couple the plurality of vertices with each other via the at least one pseudo vertex, in order to generate the second conflict graph.

12. The system of claim 8 , wherein the at least one pseudo vertex has an odd number of pseudo vertices, and on condition that the patterns corresponding to the plurality of vertices are determined to be assigned with the same color pattern, the processor is further configured to execute the computer program codes in the memory to:
add the odd number of pseudo vertices between the plurality of vertices; and
couple the plurality of vertices with each other via the odd number of pseudo vertices, in order to generate the second conflict graph.

13. The system of claim 8 , wherein on condition that the patterns corresponding to the plurality of vertices are determined to be assigned with different color patterns, the processor is further configured to execute the computer program codes in the memory to:
couple the plurality of vertices with each other, in order to generate the second conflict graph.

14. The system of claim 13 , wherein the plurality of vertices are directly coupled with each other.

15. The system of claim 8 , wherein the at least one pseudo vertex has an even number of pseudo vertices, and on condition that the patterns corresponding to the plurality of vertices are determined to be assigned with different color patterns, the processor is further configured to execute the computer program codes in the memory to:
add the even number of pseudo vertices between the plurality of vertices; and
couple the plurality of vertices with each other via the even number of pseudo vertices, in order to generate the second conflict graph.

16. A system, comprising:
a memory configured to store computer program codes;
a processor configured to execute the computer program codes in the memory to:
based on a color patterns assignment for a first pattern and a second pattern in a layout, couple a first vertex correspon

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Yen-Hung
• Hou Yuan-Te
• Hsu Chin-Chang

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F1/70 Primary

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title