Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework

Patent metadata

Field	Value
Publication number	US-10197908-B2
Application number	US-201615188910-A
Country	US
Kind code	B2
Filing date	Jun 21, 2016
Priority date	Jun 21, 2016
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

First claim

The invention claimed is:

1. A method of generating a proximity-corrected design layout for photoresist to be used in an etch operation, the method comprising:
(a) receiving an initial design layout;
(b) identifying a feature in the initial design layout, the feature's pattern corresponding to a feature that would be etched into a material stack on a semiconductor substrate's surface via a plasma-based etch process, performed in a processing chamber under a set of process conditions, when said material stack is overlaid with a layer of photoresist pattern corresponding to the initial design layout;
(c) estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature at a time t during such a plasma-based etch process;
(d) estimating a quantity characteristic of edge placement error (EPE) of the edge of the feature at time t by comparing the one or more quantities characteristic of the IFPF estimated in (c) to those in a look-up table (LUT) which associates values of the quantity characteristic of EPE at time t with values of the one or more quantities characteristics of the IFPF;
(e) modifying the initial design layout based on the quantity characteristic of EPE; and
(f) forming a mask based on a modified design layout produced in (e) and/or providing a photoresist on the material stack, wherein the photoresist contains a pattern based on the modified design layout,
wherein the LUT was constructed by running a computerized etch profile model (EPM) under the set of process conditions at least to time t on a calibration pattern of photoresist overlaid on the material stack.

2. The method of claim 1 , further comprising:
repeating (b) through (d) for one or more additional features whose patterns are in the initial design layout; and

wherein modifying the initial design layout in (e) is further based on the estimated quantity characteristic of EPE of these one or more additional features.

3. The method of claim 1 , wherein in (c) the one or more quantities characteristic of the IFPF comprise:
a quantity characteristic of in-feature plasma ion flux (IFPIF); and
a quantity characteristic of in-feature plasma neutral flux (IFPNF).

4. The method of claim 3 , wherein the quantity characteristic of IFPNF is a loaded plasma flux above the feature which accounts for the presence of the substrate in the processing chamber.

5. The method of claim 4 , wherein the loaded plasma flux is estimated in (c) based on one or more quantities characteristic of far-field global plasma fluxes in the processing chamber.

6. The method of claim 5 , wherein the one or more quantities characteristic of far-field global plasma fluxes are calculated with a computerized plasma model which accounts for processing chamber conditions but does not account for the presence of the substrate in the processing chamber.

7. The method of claim 3 , wherein the quantity characteristic of the IFPIF is estimated in (c) based on a visibility kernel (VC) corresponding to the feature.

8. The method of claim 7 , wherein the quantity characteristic of the IFPIF is calculated by a procedure comprising estimating the integral of the VC with the ion energy angular distribution function (IEADF) corresponding to one or more plasma ion fluxes (PIF) above the feature.

9. The method of claim 8 , wherein the IEADF is estimated based on one or more quantities characteristic of far-field global plasma fluxes in the processing chamber which are calculated with a computerized plasma model which accounts for processing chamber conditions.

10. The method of claim 9 , wherein the VC is estimated in (c) by assuming the feature has an opening corresponding to the initial design layout of photoresist and has substantially vertical sidewalls extending downward from the edges of the opening.

11. The method of claim 10 , further comprising:
(c′) re-estimating the VC of the feature based on the EPE estimated in (d);
(d′) re-estimating the quantity characteristic of EPE at time t by comparing the value of the visibility kernel re-estimated in (c′) to those in the LUT; and wherein the initial design layout is modified in (e) further based on the re-estimated value of the quantity characteristic of EPE at time t from (d′).

12. The method of claim 3 , wherein the LUT comprises a list of entries, at least some of the entries comprising fields for the quantity characteristic of IFPIF, the quantity characteristic of IFPNF, and the corresponding quantity characteristic of EPE.

13. The method of claim 12 , wherein at least some of the entries in the LUT further comprises one or more fields for etch time and/or feature depth.

14. The method of claim 12 , wherein at least some of the entries in the LUT further comprises a field for in-feature passivant deposition flux (IFPDF).

15. The method of claim 12 , wherein at least some of the entries in the LUT further comprise a field for edge shape indicator which corresponds to an edge shape present in the calibration pattern.

16. The method of claim 15 , wherein the method further comprises determining an edge shape indicator for the feature to be etched by pattern matching the shape of said feature against the shapes of the features present in the calibration pattern, and using said determined edge shape indicator as a basis for searching the LUT.

17. The method of claim 16 , wherein the LUT is searched first based on the feature's determined edge shape indicator.

18. The method of claim 12 :
wherein the LUT has been sorted based on one or more fields of the entries;
wherein the comparing in (d) comprises searching the LUT; and
wherein the estimating in (d) comprises interpolating between entries in the LUT after the searching.

19. The method of claim 18 , wherein the interpolating comprises a polynomial-based interpolation scheme.

20. The method of claim 1 , wherein the quantity characteristic of EPE is estimated in (d) using a trained machine learning model (MLM) which during operation:
compares one or more quantities characteristic of IFPF to those in the LUT; and
interpolates between values in the LUT;

wherein the MLM was trained on a dataset generated by running the computerized EPM, at least a subset of which was used to construct the LUT.

21. The method of claim 1 ,
wherein (c) and (d) are performed for t=t 1 to estimate a quantity characteristic of EPE at time t 1 ; and
wherein the method further comprises performing (c) and (d) for t=t 2 (>t 1 ), to estimate a quantity characteristic of EPE at time t 2 ;
wherein the initial design layout is modified in (e) based on the estimated values of the quantity characteristic of EPE at times t 1 and t 2 ; and
wherein the LUT was constructed by running the EPM at least to time t 2 .

22. A method of generating a mask design, the method comprising:
generating a proximity-corrected design layout for photoresist using the method of claim 1 ;
generating a mask design based on the generated proximity-corrected photoresist design layout.

23. A method of etching a semiconductor substrate, the method comprising:
generating a mask design using the method of claim 22 ;
forming the mask based on the mask design;
performing a photolithography operation using the mask to provide the photoresist on the material stack, wherein the photoresist pattern substantially conforms to the proximity-corrected photoresist design layout; and
exposing the substrate to a plasma which e

Assignees

• Lam Res Corp

Inventors

• Sriraman Saravanapriyan
• Wise Richard
• Singh Harmeet
• Paterson Alex
• Bailey Iii Andrew D
• Vahedi Vahid
• Gottscho Richard A

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F2115/06

  Structured ASICs · CPC title

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title