Merged pillar structures and method of generating layout diagram of same

Patent metadata

Field	Value
Publication number	US-10515178-B2
Application number	US-201815882188-A
Country	US
Kind code	B2
Filing date	Jan 29, 2018
Priority date	Aug 30, 2017
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A method (of generating a layout diagram of a conductive line structure includes: determining that a first set of first to fourth short pillar patterns (which represent portions of an M(i) layer of metallization and are located relative to a grid), violates a minimum transverse-routing (TVR) distance of alpha-direction-separation, wherein (1) the grid has orthogonal alpha and beta tracks, and (2) the short pillar patterns have long axes which are substantially co-track aligned with a first one of the alpha tracks and have a first distance (of alpha-direction-separation between immediately adjacent members of the first set) which is less than the TVR distance; and merging pairings of the first & second and third & fourth short pillar patterns into corresponding first and second medium pillar patterns which have a second distance of alpha-direction-separation therebetween; the second value being greater than the TVR distance.

First claim

What is claimed is:

1. A method of generating a revised layout diagram of a conductive line structure for an integrated circuit (IC), the method comprising:
for a first set of short pillar patterns, which is included in an initial layout diagram that is stored on a non-transitory computer-readable medium, which represents portions of an M(i) layer of metallization and where i is a non-negative integer, and which includes first to fourth short pillar patterns that are non-overlapping of each other, long axes of symmetry of the first to fourth short pillar patterns being substantially collinear with a reference line,
determining a first distance of separation as between corresponding immediately adjacent members of the first set;

recognizing that the first distance is less than a transverse routing (TVR) separation threshold for the M(i) layer;
merging pairings of the first & second and third & fourth short pillar patterns into corresponding first and second medium pillar patterns which are non-overlapping of each other, which have long axes of symmetry that are substantially collinear with the reference line, and which have a second distance of separation; and
setting the second distance to be greater than the TVR separation threshold of the M(i) layer, resulting in the revised layout diagram; and
wherein at least one of the determining, merging and setting is executed by a processor of a computer.

2. The method of claim 1 , further comprising:
fabricating, based on the revised layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of an inchoate semiconductor integrated circuit.

3. The method of claim 1 , wherein:
the first distance is represented by a variable S 1 ;
the second distance is represented by a variable S 2 ;
the first distance S 1 is equal to a minimum end-of-line spacing, S EOL , of a process-node used for manufacturing the conductive line structure corresponding to the revised layout diagram; and
the second distance S 2 has a range such that
≈(4/3)* S EOL ≤S 2≤≈2 *S EOL .

4. The method of claim 1 , the method further comprising:
recognizing that the second distance is less than a TVR separation threshold for an M(i+j) layer of metallization, where j is an integer and j≥2;
increasing the second distance so as to become a third distance; and
setting the third distance to be greater than the TVR separation threshold of the M(i+j) layer.

5. The method of claim 4 , wherein:
the first distance is represented by a variable S 1 ;
the third distance is represented by a variable S 3 ;
the first distance S 1 equal to a minimum end-of-line spacing, S EOL , of a process-node used for manufacturing the conductive line structure corresponding to the revised layout diagram; and
the third distance S 3 has a range such that
≈(7/3)* S EOL ≤S 2≤≈3 *S EOL .

6. The method of claim 4 , further comprising:
recognizing that the third distance is less than a TVR separation threshold for an M(i+j+k) layer of metallization, where k is an integer and k≥2; and
increasing the third distance so as to become a fourth distance; and
setting the fourth distance to be greater than the TVR separation threshold of the M(i+j+k) layer.

7. The method of claim 6 , wherein:
the fourth distance is represented by a variable S 4 ; and
the fourth distance has a range such that
≈(13/3)* S EOL ≤S 2≤≈5 *S EOL .

8. The method of claim 1 , the method further comprising:
setting the first and second medium pillar patterns to be a first length along the reference line;
recognizing that the second distance is less than a TVR separation threshold for an M(i+j) layer of metallization, where j is an integer and j≥2; and
decreasing the first length so as to become a second length; and
wherein the second length is smaller than the first length.

9. The method of claim 8 , wherein:
a length along the reference line of each of the first to fourth short pillar patterns is a third length; and
the third length is smaller than the second length.

10. A system for revising a layout diagram of a conductive line structure for an integrated circuit (IC), the system comprising:
at least one processor; and
at least one non-transitory computer-readable medium (NTCRM) including computer program code for one or more programs;
wherein the at least one NTCRM, the computer program code and the at least one processor are configured to cause the system to:
for a first set of short pillar patterns which is included in an initial layout diagram that is stored in the at least one NTCRM, which represents portions of an M(i) layer of metallization and where i is a non-negative integer, and which includes first to fourth short pillar patterns that are non-overlapping of each other and have long axes of symmetry that are substantially collinear with a first reference line,
determine a first distance of separation as between corresponding immediately adjacent members of the first set;

recognize that the first distance is less than a transverse routing (TVR) separation threshold for the M(i) layer; and
merge pairings of the first & second and third & fourth short pillar patterns into corresponding first and second medium pillar patterns which are non-overlapping of each other, which have long axes of symmetry that are substantially collinear with the first reference line, and which have a second distance of separation, the second distance being greater than the first distance;
recognize that the second distance is less than a TVR separation threshold for an M(i+j) layer of metallization, where j is an integer and j≥2; and

increase the second distance to a third distance, the third distance being equal to or greater than the TVR separation threshold for the M(i+j) layer, resulting in a revised layout diagram.

11. The system of claim 10 , further comprising:
a facility to fabricate, based on the revised layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of an inchoate semiconductor integrated circuit.

12. The system of claim 10 , wherein the at least one NTCRM, the computer program code and the at least one processor are further configured to cause the system to:
recognize that the third distance is less than a TVR separation threshold for an M(i+j+k) layer of metallization, where k is an integer and k≥2;
increase the third distance so as to become a fourth distance; and
set the fourth distance to be greater than the TVR separation threshold of the M(i+j+k) layer.

13. The system of claim 10 , the wherein at least one NTCRM, the computer program code and the at least one processor are further configured to cause the system to:
set the first and second medium pillar patterns to be a first length along the first reference line;
recognize that the third distance is less than a TVR separation threshold for an M(i+j) layer of metallization, where j is an integer and j≥2; and
decrease the first length so as to become a second length; and
wherein the second length is smaller than the first length.

14. The system of claim 13 , wherein:
a length along the first reference line of each of the first to fourth short pillar patterns is a third length; and
the third length is smaller than the second length.

15. The system of claim 10 , wherein:
the initial layout diagram further includes:
a second set of fifth to eighth short pillar patterns, the fifth to eighth short pillar patterns:
representing portions of an M(i+1) layer of metallization;
being non-overlapping of each ot

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Biswas Hiranmay
• Wang Chung-Hsing
• Yang Kuo-Nan
• Cheng Yi-Kan

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2115/06

  Structured ASICs · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title