Semiconductor devices having a gate isolation layer and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-RE50699-E
Application number	US-202318112544-A
Country	US
Kind code	E1
Filing date	Feb 22, 2023
Priority date	Jun 12, 2018
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

Semiconductor devices are provided. A semiconductor device includes a channel region that protrudes from a substrate. The semiconductor device includes a gate line on the channel region. Moreover, the semiconductor device includes a gate isolation layer that is between a first portion of the gate line and a second portion of the gate line. The gate isolation layer is in contact with the gate line and includes a gap that is in the gate isolation layer. Related methods of manufacturing a semiconductor device are also provided.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first channel region and a second channel region that protrude from a substrate and that extend in a first direction; a first gate on the first channel region; a second gate on the second channel region, wherein the first gate and the second gate extend in a second direction intersecting the first direction and are spaced apart from each other in the second direction; a first gate insulating layer between the first gate and the first channel region; a second gate insulating layer between the second gate and the second channel region; and a gate isolation layer between the first gate and the second gate, wherein the gate isolation layer is in contact with the first gate and the second gate and comprises a gap that is in the gate isolation layer, wherein a first width of the gate isolation layer in the second direction is greater than a second width of the gate isolation layer in the second direction, wherein a third width of the gate isolation layer in the second direction is less than the first width of the gate isolation layer, wherein the first width is located between the second width and the third width in a vertical direction, wherein the second width is at a level that is coplanar with an upper surface of the first gate, and wherein the gate isolation layer monotonically decreases in width from the first width to the second width.

2 . The semiconductor device of claim 1 ,
wherein the first gate insulating layer and the second gate insulating layer are spaced apart from each other with the gate isolation layer therebetween, and wherein the gate isolation layer is in contact with the first gate and the second gate at each of the first width, the second width, and the third width.

3 . The semiconductor device of claim 1 , wherein a top end of the gap is at a higher level than a top end of the first channel region.

4 . The semiconductor device of claim 1 ,
wherein the first gate insulating layer is on a first side surface and a second side surface of the first gate, and wherein the second gate insulating layer is on a first side surface and a second side surface of the second gate.

5 . The semiconductor device of claim 1 , further comprising a device isolation layer that is in a trench between the first channel region and the second channel region,
wherein the first gate insulating layer is between the first gate and the device isolation layer, wherein the second gate insulating layer is between the second gate and the device isolation layer, wherein an upper portion of the device isolation layer comprises a recess, wherein a portion of the gate isolation layer is in the recess, and wherein a bottom end of the gate isolation layer is at a lower level than a top end of the device isolation layer.

6 . The semiconductor device of claim 5 , wherein a bottom end of the gap is at a lower level than the top end of the device isolation layer.

7 . The semiconductor device of claim 1 ,
wherein the gap comprises an air gap that has an elliptical shape, and wherein a middle portion of the air gap is wider in the second direction than upper and lower portions of the air gap.

8 . The semiconductor device of claim 1 , wherein, when viewed in a vertical cross-section, a sidewall of the gate isolation layer comprises a plurality of bulges.

9 . The semiconductor device of claim 1 , further comprising a first capping layer and a second capping layer on the first gate and the second gate, respectively, the first capping layer and the second capping layer being spaced apart from each other in the second direction with the gate isolation layer therebetween,
wherein a width between respective bottom ends of the first capping layer and the second capping layer is greater than a width between respective top ends of the first capping layer and the second capping layer, and a top end of the gap is at a higher level than the bottom end of the first capping layer and the bottom end of the second capping layer.

10 . A semiconductor device comprising:
a substrate comprising a channel region that protrudes from the substrate; a gate line on a first side surface and a second side surface of the channel region; gate spacers on a first side surface and a second side surface of the gate line; and a gate isolation layer in a gate cut region that separates a first portion of the gate line from a second portion of the gate line, wherein the gate isolation layer is in contact with the gate line and comprises a gap that is in the gate isolation layer, wherein a first width of the gap is greater than a second width of the gap, wherein a third width of the gap is narrower than the first width, wherein the first width is located between the second width and the third width, wherein a first distance between the first and second portions of the gate line at a middle portion of the gate isolation layer is greater than a second distance between the first and second portions of the gate line adjacent a top end of the gate isolation layer, wherein the gate line comprises one among a plurality of gate lines spaced apart from each other in a first direction that intersects a second direction in which the first portion of the gate line is separated from the second portion of the gate line, wherein the gate cut region extends in the first direction into at least two of the plurality of gate lines, wherein the gate isolation layer extends in the first direction in the gate cut region, wherein the gap is at an intersection between the gate isolation layer and the gate line, and wherein a portion of the gate cut region that is between the at least two of the plurality of gate lines increases in width toward a middle of the portion of the gate cut region.

11 . The semiconductor device of claim 10 , wherein the gate cut region separates the gate spacers.

12 . The semiconductor device of claim 10 , wherein the gate cut region has an elliptical shape.

13 . The semiconductor device of claim 10 , further comprising a gate insulating layer between the gate line and the gate spacers.

14 . The semiconductor device of claim 10 , wherein a first width of the gate cut region in the gate line is greater than a second width of the gate cut region between the at least two of the plurality of gate lines.

15 . The semiconductor device of claim 10 ,
wherein a top end of the gap is at a higher level than a top end of the channel region, and wherein the gap extends a majority of a height of the gate cut region.

16 . The semiconductor device of claim 10 ,
wherein the gap comprises an air gap that has an elliptical shape, and wherein a middle portion of the air gap is wider than upper and lower portions of the air gap.

17 . A semiconductor device comprising:
a substrate comprising a channel region that protrudes from the substrate and that extends in a first direction; a first gate line and a second gate line that are on the channel region and that extend in a second direction intersecting the first direction, wherein the first gate line is spaced apart from the second gate line in the first direction; gate spacers on a first side surface and a second side surface of the first gate line; a gate insulating layer between the first gate line and the gate spacers; a gate isolation layer in a gate cut region that is between the first gate line and the second gate line in the first direction; and a gap in the gate isolation layer, wherein the gate cut region separates the first gate line, sepa

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Yong Ho
• Kim Jung Hyun
• Myung Sung Woo
• Oh Young Mook
• Lee Dong Seok

Classifications

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title