Multiple Fin FET structures having an insulating separation plug

Patent metadata

Field	Value
Publication number	US-9601567-B1
Application number	US-201514928214-A
Country	US
Kind code	B1
Filing date	Oct 30, 2015
Priority date	Oct 30, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first fin field-effect transistor (Fin FET) including a first fin structure extending in a first direction and a first gate structure, the first gate structure including a first gate dielectric layer formed over the first fin structure and a first gate electrode layer formed over the first gate dielectric layer and extending in a second direction perpendicular to the first direction; and
a second Fin FET including a second fin structure extending in the first direction and a second gate structure, the second gate structure including a second gate dielectric layer formed over the second fin structure and a second gate electrode layer formed over the second gate dielectric layer and extending in the second direction, wherein:
the first gate structure and the second gate structure are aligned along the second direction,
the first gate structure and the second gate structure are separated by a separation plug made of an insulating material, and
the first gate electrode layer is in contact with a side wall of the separation plug without interposing the first gate dielectric layer therebetween.

2. The semiconductor device of claim 1 , wherein:
the first gate electrode layer includes underlying layers and a main metal electrode layer formed over the first fin structure, and
the main metal electrode layer is in contact with the side wall of the separation plug.

3. The semiconductor device of claim 1 , wherein the separation plug is made of a silicon nitride based material.

4. The semiconductor device of claim 1 , wherein:
the second gate electrode layer includes underlying layers and a main metal electrode layer formed over the second fin structure, and
the main metal electrode layer of the second gate electrode layer is in contact with a side wall of the separation plug.

5. The semiconductor device of claim 1 , wherein an uppermost portion of the first gate dielectric layer along the second direction is located above the first fin structure.

6. The semiconductor device of claim 2 , wherein uppermost portions of the underlying layers along the second direction are located above the first fin structure.

7. The semiconductor device of claim 1 , wherein:
the first gate structure has a first end and a second end,
the separation plug is provided at the first end, and
another separation plug is provided at the second end.

8. The semiconductor device of claim 1 , wherein:
the first gate structure has a first end and a second end,
the separation plug is provided at the first end, and
no separation plug is provided at the second end.

9. The semiconductor device of claim 8 , wherein
at the second end, the first gate electrode layer is not in contact with a side wall of the another separation plug.

10. A semiconductor device, comprising:
a first field effect transistor (FET) including a first channel region of a semiconductor substrate and a first gate structure, the first gate structure including a first gate dielectric layer formed over the first channel region and a first gate electrode layer formed over the first gate dielectric layer and extending in a first direction; and
a second FET including a second channel region of the semiconductor substrate and a second gate structure, the second gate structure including a second gate dielectric layer formed over the second channel region and a second gate electrode layer formed over the second gate dielectric layer and extending in the first direction, wherein:
the first gate structure and the second gate structure are aligned along the first direction,
the first gate structure and the second gate structure are separated by a separation plug made of an insulating material, and
the first gate electrode layer is in contact with a side wall of the separation plug without interposing the first gate dielectric layer therebetween.

11. The semiconductor device of claim 10 , wherein:
the first gate electrode layer includes underlying layers and a main metal electrode layer formed over the first channel region, and
the main metal electrode layer is in contact with the side wall of the separation plug.

12. The semiconductor device of claim 10 , wherein the separation plug is made of a silicon nitride based material.

13. The semiconductor device of claim 10 , wherein:
the second gate electrode layer includes underlying layers and a main metal electrode layer formed over the second channel region, and
the main metal electrode layer of the second gate electrode layer is in contact with a side wall of the separation plug.

14. The semiconductor device of claim 10 , wherein an uppermost portion of the first gate dielectric layer along the second direction is located above the first channel region.

15. The semiconductor device of claim 11 , wherein uppermost portions of the underlying layers along the second direction are located above the first channel region.

16. The semiconductor device of claim 10 , wherein:
the first gate structure has a first end and a second end,
the separation plug is provided at the first end, and
another separation plug is provided at the second end.

17. The semiconductor device of claim 10 , wherein:
the first gate structure has a first end and a second end,
the separation plug is provided at the first end, and
no separation plug is provided at the second end.

18. The semiconductor device of claim 17 , wherein
at the second end, the first gate electrode layer is not in contact with a side wall of the another separation plug.

19. A semiconductor device, comprising:
a first field effect transistor (FET) including a channel region of a semiconductor substrate and a gate structure, the gate structure including a gate dielectric layer formed over the channel region and a gate electrode layer formed over the gate dielectric layer and extending in a first direction; and
a first insulating plug and a second insulating plug disposed on both sides of the gate electrode layer along the first direction,
wherein, in a cross section along the first direction, the gate electrode layer is in contact with at least a side wall of the first insulating plug without interposing the gate dielectric layer therebetween.

20. The semiconductor device of claim 19 ,
wherein, in the cross section along the first direction, the gate dielectric layer is interposed between the gate electrode layer and the second insulating plug.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsieh Chih-Hung

Classifications

• H10P50/264

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D64/01326 Primary

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10D30/6215

  having multiple independently-addressable gate electrodes · CPC title

• H10D30/795

  being in lateral device isolation regions, e.g. STI · CPC title