Structure and formation method of semiconductor device structure

Patent metadata

Field	Value
Publication number	US-9553090-B2
Application number	US-201514725555-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	May 29, 2015
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

First claim

What is claimed is:

1. A semiconductor device structure, comprising:
a fin structure over a semiconductor substrate;
a gate stack covering a portion of the fin structure, wherein the gate stack comprises a work function layer and a metal filling over the work function layer; and
an isolation element over the semiconductor substrate and adjacent to the gate stack, wherein the isolation element is in direct contact with the work function layer and the metal filling, and a top surface of the isolation element is substantially coplanar with a top surface of the gate stack.

2. The semiconductor device structure as claimed in claim 1 , wherein the gate stack comprises a gate dielectric layer between the fin structure and the work function layer, and the gate dielectric layer is in direct contact with the isolation element.

3. The semiconductor device structure as claimed in claim 1 , further comprising an isolation feature between the semiconductor substrate and the gate stack, wherein the isolation element is in direct contact with the isolation feature.

4. The semiconductor device structure as claimed in claim 1 , further comprising a dielectric layer over the semiconductor substrate and surrounding the gate stack and the isolation element.

5. The semiconductor device structure as claimed in claim 1 , wherein the isolation element has an upper side and a lower side between the upper side and the semiconductor substrate, and the lower side is wider than the upper side.

6. The semiconductor device structure as claimed in claim 1 , further comprising spacer elements adjacent to the gate stack and the isolation element, wherein the gate stack and the isolation element are sandwiched between the spacer elements.

7. The semiconductor device structure as claimed in claim 6 , wherein the metal filling is not in direct contact with the spacer elements.

8. The semiconductor device structure as claimed in claim 1 , wherein a width of the work function layer is different from that of the metal filling.

9. A semiconductor device structure, comprising:
a first fin structure and a second fin structure over a semiconductor substrate;
a first gate stack covering a portion of the first fin structure;
a second gate stack covering a portion of the second fin structure; and
an isolation element over the semiconductor substrate and between the first gate stack and the second gate stack, wherein the isolation element is in direct contact with a first work function layer and a first metal filling of the first gate stack and a second work function layer and a second metal filling of the second gate stack, and a top surface of the isolation element is substantially coplanar with a top surface of the first gate stack.

10. The semiconductor device structure as claimed in claim 9 , wherein the first work function layer and the second work function layer are a p-type metal layer and an n-type metal layer, respectively.

11. The semiconductor device structure as claimed in claim 9 , further comprising:
a first gate dielectric layer between the first fin structure and the first work function layer; and
a second gate dielectric layer between the second fin structure and the second work function layer, wherein the isolation element is in direct contact with the first gate dielectric layer and the second gate dielectric layer.

12. The semiconductor device structure as claimed in claim 11 , wherein materials of the first gate dielectric layer and the second gate dielectric layer are the same.

13. The semiconductor device structure as claimed in claim 9 , further comprising an isolation feature between the semiconductor substrate and the first gate stack, wherein the isolation element is in direct contact with the isolation feature.

14. The semiconductor device structure as claimed in claim 9 , wherein an angle between a sidewall of the isolation element and a lower side of the isolation element is in a range from about 10 degrees to about 85 degrees.

15. The semiconductor device structure as claimed in claim 9 , wherein the isolation element has an upper side and a lower side between the upper side and the semiconductor substrate, and the lower side is wider than the upper side.

16. The semiconductor device structure as claimed in claim 9 , further comprising dielectric layer over the semiconductor substrate and surrounding the first gate stack, the second gate stack, and the isolation element.

17. The semiconductor device structure as claimed in claim 16 , wherein materials of the dielectric layer and the isolation element are different from each other.

18. The semiconductor device structure as claimed in claim 9 , wherein materials of the first metal filling and the second metal filling are the same.

19. The semiconductor device structure as claimed in claim 9 , further comprising spacer elements adjacent to the first gate stack and the isolation element, wherein the first gate stack and the isolation element are sandwiched between the spacer elements.

20. The semiconductor device structure as claimed in claim 7 , wherein the spacer elements are in direct contact with a second gate stack, and the second gate stack are sandwiched between the spacer elements.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Cheng
• Chuang Jui-Ping
• Lu Chen-Hsiang
• Chen Wei-Ting
• Liu Yu-Cheng

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/0653

  Electricity · mapped topic

• H01L29/42372

  Electricity · mapped topic