Airgap spacers

Patent metadata

Field	Value
Publication number	US-9673293-B1
Application number	US-201615047123-A
Country	US
Kind code	B1
Filing date	Feb 18, 2016
Priority date	Feb 18, 2016
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Semiconductor devices with airgap spacers and methods of forming the same include forming a lower spacer that defines a gate region. A sacrificial upper spacer is formed directly above the lower spacer. A gate stack is formed in the gate region. The sacrificial upper spacer is etched away to form an upper spacer opening. An airgap spacer is formed in the upper spacer opening. The airgap spacer includes a dielectric material that encapsulates an internal void.

First claim

What is claimed is:

1. A method for forming a semiconductor device, comprising:
forming one or more semiconductor fins on a substrate;
forming a first dummy gate across the one or more semiconductor fins;
forming a second dummy gate over the first dummy gate, wherein a material of the first dummy gate is different from a material of the second dummy gate;
forming an initial spacer around the first and second dummy gates;
forming a lower spacer that defines a gate region by etching the initial spacer down to a top level of the one or more semiconductor fins;
forming a sacrificial upper spacer directly above the lower spacer;
forming a gate stack in the gate region;
etching away the sacrificial upper spacer to form an upper spacer opening; and
forming an airgap spacer in the upper spacer opening that comprises a dielectric material that encapsulates an internal void.

2. The method of claim 1 , wherein the first dummy gate has a height greater than a height of the one or more semiconductor fins.

3. The method of claim 1 , further comprising depositing an interlayer dielectric layer around the initial spacer.

4. The method of claim 1 , further comprising etching away the second dummy gate before forming the lower spacer.

5. The method of claim 4 , further comprising etching away the first dummy gate after forming the sacrificial upper spacer.

6. The method of claim 1 , wherein forming the airgap spacer comprises non-conformally depositing a dielectric material that seals off a top opening of the upper spacer opening.

7. The method of claim 1 , wherein the dielectric material comprises a composition of silicon, oxygen, carbon, and nitrogen (SiOCN).

8. The method of claim 1 , wherein forming the airgap spacer comprises depositing the dielectric material using plasma enhanced chemical vapor deposition.

9. A method for forming a semiconductor device, comprising:
forming a first dummy gate across one or more semiconductor fins on a substrate, wherein the first dummy gate has a height greater than a height of the one or more semiconductor fins;
forming a second dummy gate over the first dummy gate, wherein a material of the first dummy gate is different from a material of the second dummy gate;
forming an initial spacer around the first and second dummy gates;
depositing an interlayer dielectric layer around the initial spacer;
etching away the second dummy gate;
forming a lower spacer after etching away the second dummy gate by etching the initial spacer down to a top level of the one or more semiconductor fins;
forming a sacrificial upper spacer directly above the lower spacer;
etching away the first dummy gate;
forming a gate stack in the gate region defined by the lower spacer and the sacrificial upper spacer;
etching away the sacrificial upper spacer to form an upper spacer opening; and
forming an airgap spacer in the upper spacer opening by non-conformally depositing a dielectric material comprising a composition of silicon, oxygen, carbon, and nitrogen (SiOCN) to seal off a top opening of the upper spacer opening and to encapsulate an internal void.

10. The method of claim 9 , wherein the first dummy gate has a height greater than a height of the one or more semiconductor fins.

11. The method of claim 9 , wherein forming the airgap spacer comprises depositing the dielectric material using plasma enhanced chemical vapor deposition.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Liu Zuoguang
• Yeung Chun W

Classifications

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H01L21/823821

  Electricity · mapped topic

• H01L29/4991 Primary

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/161

  Electricity · mapped topic