Gate-all-around fin device

Patent metadata

Field	Value
Publication number	US-9978874-B2
Application number	US-201715402504-A
Country	US
Kind code	B2
Filing date	Jan 10, 2017
Priority date	Nov 19, 2014
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

First claim

What is claimed:

1. A method comprising:
forming a plurality of fin structures from a substrate;
forming a well of a first conductivity type and a well of a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures;
forming a source contact on an exposed portion of a first fin structure of the plurality of fin structures;
forming drain contacts on exposed portions of second fin structures of the plurality of fin structures, wherein the second fin structures are adjacent to the first fin structure; and
forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type, wherein:
the well of the first conductivity type is formed as a shallow N-well and the well of the second conductivity type is formed as a P-well, and
the gate structure is formed partially over the shallow N-well and the P-well.

2. The method of claim 1 , wherein the shallow N-well is a ring structure.

3. The method of claim 2 , wherein the dielectric fill material extends between the first fin structure and the second fin structures.

4. The method of claim 3 , wherein the dielectric fill material overlaps a portion of an upper surface of the shallow N-well and a portion of the P-well.

5. The method of claim 1 , further comprising forming the source contact and the drain contacts by an epitaxial growth process followed by an n+ implantation process.

6. The method of claim 1 , wherein the forming of the plurality of fin structures includes forming body contact fins.

7. The method of claim 1 , wherein the second fin structures and the drain contacts are formed over the shallow N-well.

8. The method of claim 7 , further comprising forming third fin structures of the plurality of fin structures, wherein the second fin structures are interposed between the first fin structure and the third fin structures.

9. The method of claim 8 , wherein the third fin structures are formed above the P-well.

10. The method of claim 9 , further comprising forming P-well contacts over the third fin structures.

11. The method of claim 10 , wherein the dielectric fill material extends between the second fin structures and the third fin structures.

12. A semiconductor device comprising:
a plurality of fin structures formed on a substrate;
a well of a first conductivity type and a well of a second conductivity type formed within the substrate and corresponding fin structures of the plurality of fin structures;
a source contact formed on an exposed portion of a first fin structure of the plurality of fin structures;
drain contacts formed on exposed portions of second fin structures of the plurality of fin structures, wherein the second fin structures are adjacent to the first fin structure; and
a gate structure formed in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type, wherein:
the well of the first conductivity type is formed as a shallow N-well and the well of the second conductivity type is formed as a P-well, and
the gate structure is formed partially over the shallow N-well and the P-well.

13. The device of claim 12 , wherein the shallow N-well is a ring structure.

14. The device of claim 13 , wherein the dielectric fill material extends between the first fin structure and the second fin structures.

15. The device of claim 14 , wherein the dielectric fill material overlaps a portion of an upper surface of the shallow N-well and a portion of the P-well.

16. The device of claim 12 , wherein the second fin structures and the drain contacts are formed over the shallow N-well.

17. The device of claim 16 , further comprising third fin structures of the plurality of fin structures, wherein the second fin structures are interposed between the first fin structure and the third fin structures.

18. The device of claim 17 , wherein the third fin structures are formed above the P-well.

19. The device of claim 18 , further comprising P-well contacts formed over the third fin structures.

20. The device of claim 19 , wherein the dielectric fill material extends between the second fin structures and the third fin structures.

Assignees

• IBM

Inventors

• Campi Jr John B
• Gauthier Jr Robert J
• Mishra Rahul
• Mitra Souvick
• Muhammad Mujahid

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01G4/20

  using combinations of dielectrics from more than one of groups H01G4/02 - H01G4/06 (H01G4/12 takes precedence) · CPC title

• H01G4/206

  inorganic and synthetic material · CPC title