Gate-all-around fin device

Patent metadata

Field	Value
Publication number	US-2016284852-A1
Application number	US-201615171288-A
Country	US
Kind code	A1
Filing date	Jun 2, 2016
Priority date	Nov 19, 2014
Publication date	Sep 29, 2016
Grant date	—

Abstract

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

First claim

What is claimed:

1 . A structure comprising:
a substrate of a first conductivity type; a doped well located in the substrate of the first conductivity type; a doped well ring of a second conductivity type and enclosing a central well of the first conductivity type; a first doped fin contact region of the first conductivity type forming a source contact to a gate structure over the central well of the first conductivity type; and a second doped fin contact region of the second conductivity type forming drain regions to the gate structure, the second doped fin contact region being formed over the doped well ring, wherein the drain regions include alternating p regions and n regions formed directly on the second doped fin contact region.

2 . The structure of claim 1 , wherein the gate structure is in a dielectric fill material.

3 . The structure of claim 1 , further comprising a shallow trench isolation (STI) structure in the doped well.

4 . The structure of claim 1 , wherein the doped well is of the first conductivity type.

5 . The structure of claim 4 , wherein:
the first conductivity type is formed as a deep N-well and the second conductivity type as a P-well; and the gate structure is formed partially over the deep N-well and the P-well.

6 . The structure of claim 5 , wherein the deep N-well is formed as a ring surrounding the P-well.

7 . The structure of claim 4 , wherein:
the first conductivity type is formed as a continuous deep N-well and the second conductivity type as a P-well; and the gate structure is formed completely over the deep N-well.

8 . The structure of claim 4 , wherein:
the first conductivity type is formed as a shallow N-well and the second conductivity type is a P-well; the gate structure is formed partially over the shallow N-well and the P-well; and the shallow N-well is a ring structure.

9 . The structure of claim 4 , wherein:
the first conductivity type is formed as a continuous shallow N-well and the second conductivity type as a P-well; the gate structure is formed entirely over the shallow N-well; and the first fin structure comprising the source contact is formed completely over the shallow N-well.

10 . The structure of claim 1 , wherein the gate structure is formed over an insulating layer above the central well and is structured vertically around a fin region of the first doped fin contact region and extends laterally in the direction of and crossing over onto the doped well ring.

Assignees

• IBM

Inventors

• Campi Jr John B
• Gauthier Jr Robert J
• Mishra Rahul
• Mitra Souvick
• Muhammad Mujahid

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01G4/20

  using combinations of dielectrics from more than one of groups H01G4/02 - H01G4/06 (H01G4/12 takes precedence) · CPC title

• H01G4/206

  inorganic and synthetic material · CPC title