Gate-all-around fin device

Patent metadata

Field	Value
Publication number	US-9590108-B2
Application number	US-201614995307-A
Country	US
Kind code	B2
Filing date	Jan 14, 2016
Priority date	Nov 19, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

First claim

What is claimed:

1. A semiconductor device comprising:
a plurality of fin structures on a substrate;
a well of a first conductivity type and a well of a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures;
a source contact on an exposed portion of a first fin structure;
drain contacts on exposed portions of adjacent fin structures to the first fin structure; and
a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

2. The semiconductor device of claim 1 , further comprising a shallow trench isolation (STI) structure in the well of the first conductivity type.

3. The semiconductor device of claim 2 , wherein the STI structure and the dielectric fill material are formed in a same deposition step.

4. The semiconductor device of claim 1 , wherein the source contact and the drain contacts are formed by an epitaxial growth process followed by an n+ implantation process.

5. The semiconductor device of claim 4 , wherein:
the well of the first conductivity type is a deep N-well and the well of the second conductivity type is a P-well; and
the gate structure extends partially over the deep N-well and the P-well.

6. The semiconductor device of claim 5 , wherein the deep N-well is a ring surrounding the P-well.

7. The semiconductor device of claim 4 , wherein:
the well of the first conductivity type is a continuous deep N-well and the well of the second conductivity type is a P-well; and
the gate structure and the first fin structure comprising the source contact extend completely over the deep N-well, thereby forming a floating contact.

8. The semiconductor device of claim 4 , wherein:
the well of the first conductivity type is a shallow N-well and the well of the second conductivity type is a P-well;
the gate structure extends partially over the shallow N-well and the P-well; and
the shallow N-well is a ring structure.

9. The semiconductor device of claim 4 , wherein:
the well of the first conductivity type is a continuous shallow N-well and the well of the second conductivity type as a P-well;
the gate structure extends entirely over the shallow N-well; and
the first fin structure comprising the source contact extends completely over the shallow N-well.

10. The semiconductor device of claim 1 , wherein the plurality of fin structures includes body contact fins.

11. The semiconductor device of claim 4 , wherein:
the well of the first conductivity type is a continuous deep N-well and the well of the second conductivity type is a P-well; and
the gate structure extends completely over the deep N-well.

12. The semiconductor device of claim 6 , wherein the gate structure is configured vertically around the first fin structure and laterally extends to cross over onto the deep N-well region.

Assignees

• IBM

Inventors

• Campi Jr John B
• Gauthier Jr Robert J
• Mishra Rahul
• Mitra Souvick
• Muhammad Mujahid

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01G4/20

  using combinations of dielectrics from more than one of groups H01G4/02 - H01G4/06 (H01G4/12 takes precedence) · CPC title

• H01G4/206

  inorganic and synthetic material · CPC title