Gate-all-around fin device

US9818542B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9818542-B2
Application numberUS-201514882800-A
CountryUS
Kind codeB2
Filing dateOct 14, 2015
Priority dateNov 19, 2014
Publication dateNov 14, 2017
Grant dateNov 14, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

First claim

Opening claim text (preview).

What is claimed: 1. A method comprising: forming a plurality of fin structures from a substrate; forming a well of a first conductivity type and a well of a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures; forming a source contact on an exposed portion of a first fin structure; forming drain contacts on exposed portions of adjacent fin structures to the first fin structure; and forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type, wherein: the source contact and the drain contacts are formed by an epitaxial growth process followed by an n+ implantation process; the well of the first conductivity type is formed as a continuous deep N-well and the well second conductivity type is formed as a P-well; and the gate structure and the first fin structure comprising the source contact are formed completely over the deep N-well, thereby forming a floating contact. 2. The method of claim 1 , further comprising forming a shallow trench isolation (STI) structure in the well of the first conductivity type. 3. The method of claim 2 , wherein the STI structure and the dielectric fill material are formed in a same deposition step. 4. The method of claim 3 , wherein the STI structure is shallower than the continuous deep N-well. 5. The method of claim 4 , wherein the dielectric fill material extends between the first fin structure and the adjacent fin structures. 6. The method of claim 5 , wherein the dielectric fill material overlaps a portion of the STI structure and overlaps a portion of an upper surface of the continuous deep N-well. 7. The method of claim 1 , wherein the source contact and the drain contacts are formed by an epitaxial growth process followed by an n+ implantation process. 8. The method of claim 1 , wherein the forming of the plurality of fin structures includes forming body contact fins. 9. The method of claim 1 , wherein the adjacent fin structures and the drain contacts are formed over the deep N-type well. 10. The method of claim 2 , wherein a portion of the gate structure overlaps a portion of the STI structure. 11. The method of claim 10 , further comprising forming a deep P-band implant region under the well of the first conductivity type and the well of the second conductivity type. 12. The method of claim 11 , wherein a portion of the well of the first conductivity type extends between a lower surface of the STI structure and an upper surface of the deep P-band implant region.

Assignees

Inventors

Classifications

  • into Group IV semiconductors · CPC title

  • using masks · CPC title

  • of electrically active species · CPC title

  • using combinations of dielectrics from more than one of groups H01G4/02 - H01G4/06 (H01G4/12 takes precedence) · CPC title

  • inorganic and synthetic material · CPC title

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What does patent US9818542B2 cover?
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The met…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01G4/33. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).