Gate-all-around fin device

US2016181162A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016181162-A1
Application numberUS-201514882800-A
CountryUS
Kind codeA1
Filing dateOct 14, 2015
Priority dateNov 19, 2014
Publication dateJun 23, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

First claim

Opening claim text (preview).

What is claimed: 1 . A method comprising: forming a plurality of fin structures from a substrate; forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures; forming a source contact on an exposed portion of a first fin structure; forming drain contacts on exposed portions of adjacent fin structures to the first fin structure; and forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type, wherein: the source contact and the drain contacts are formed by an epitaxial growth process followed by an n+ implantation process; the first conductivity type is formed as a deep N-well and the second conductivity type as a P-well; the gate structure is formed partially over the deep N-well and the P-well; the first conductivity type is formed as a continuous deep N-well and the second conductivity type as a P-well; and the gate structure and the first fin structure comprising the source contact are formed completely over the deep N-well, thereby forming a floating contact. 2 . A method comprising: forming a plurality of fin structures from a substrate; forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures; forming a source contact on an exposed portion of a first fin structure; forming drain contacts on exposed portions of adjacent fin structures to the first fin structure; and forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type, wherein: the source contact and the drain contacts are formed by an epitaxial growth process followed by an n+ implantation process; the first conductivity type is formed as a deep N-well and the second conductivity type as a P-well; the gate structure is formed partially over the deep N-well and the P-well; the first conductivity type is formed as a shallow N-well and the second conductivity type is a P-well; the gate structure is formed partially over the shallow N-well and the P-well; and the shallow N-well is a ring structure. 3 . A method comprising: forming a plurality of fin structures from a substrate; forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures; forming a source contact on an exposed portion of a first fin structure; forming drain contacts on exposed portions of adjacent fin structures to the first fin structure; and forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type, wherein: the source contact and the drain contacts are formed by an epitaxial growth process followed by an n+ implantation process; the first conductivity type is formed as a deep N-well and the second conductivity type as a P-well; the gate structure is formed partially over the deep N-well and the P-well; the first conductivity type is formed as a continuous shallow N-well and the second conductivity type as a P-well; the gate structure is formed entirely over the shallow N-well; and the first fin structure comprising the source contact is formed completely over the shallow N-well.

Assignees

Inventors

Classifications

  • into Group IV semiconductors · CPC title

  • using masks · CPC title

  • of electrically active species · CPC title

  • using combinations of dielectrics from more than one of groups H01G4/02 - H01G4/06 (H01G4/12 takes precedence) · CPC title

  • inorganic and synthetic material · CPC title

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What does patent US2016181162A1 cover?
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The met…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01G4/33. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 23 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).