Forming air-gap spacer for vertical field effect transistor

Patent metadata

Field	Value
Publication number	US-9929246-B1
Application number	US-201715413558-A
Country	US
Kind code	B1
Filing date	Jan 24, 2017
Priority date	Jan 24, 2017
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A method is presented for forming a semiconductor structure. The method includes forming a fin over a bottom source/drain region, forming a high-k metal gate (HKMG) adjacent the fin, forming an epitaxial layer over the fin such that at least one gap region is defined adjacent the HKMG, and forming a top source/drain region over the epitaxial layer and the at least one gap region. A hard mask is deposited before the epitaxial layer to cover the fin and the HKMG. An inter-level dielectric (ILD) oxide is deposited adjacent the hard mask. The hard mask is etched to expose a top region of the fin to receive the epitaxial layer. At least one gap region is defined adjacent top sidewalls of the fin.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
forming a fin over a bottom source/drain region;
forming a high-k metal gate (HKMG) stack adjacent the fin;
forming an epitaxial layer on the fin, the epitaxial layer having a thickness greater than a thickness of the fin to define at least one gap region adjacent the fin; and
forming a top source/drain region on the epitaxial layer and over the at least one gap region.

2. The method of claim 1 , wherein the fin includes a nitride spacer deposited thereon.

3. The method of claim 1 , wherein a poly-open chemical polish (POC) liner is deposited over the bottom source/drain region.

4. The method of claim 1 , wherein a hard mask is deposited before the epitaxial layer to cover the fin and the HKMG stack.

5. The method of claim 4 , wherein an inter-level dielectric (ILD) oxide is deposited adjacent the hard mask.

6. The method of claim 4 , wherein the hard mask is etched to expose a top region of the fin to receive the epitaxial layer.

7. The method of claim 5 , wherein the hard mask is further etched to expose a top surface of the HKMG stack.

8. The method of claim 1 , wherein silicon nitride (SiN) is deposited within the recess created by the etching of the hard mask.

9. The method of claim 1 , wherein the at least one gap region is defined adjacent top sidewalls of the fin.

10. A method of forming an air-gap spacer for a vertical field effect transistor (VFET), the method comprising:
forming a fin over a substrate;
depositing a hard mask over the fin;
etching the hard mask to expose a top region of the fin;
forming an epitaxial layer on the top region of the fin, the epitaxial layer having a thickness greater than a thickness of the fin to define the air-gap spacer adjacent the fin; and
depositing silicon nitride (SiN) within a recess created byr the etching of the hard mask.

11. The method of claim 10 , wherein a bottom source/drain region is formed over the substrate.

12. The method of claim 11 , wherein a poly-open chemical polish (POC) liner is deposited over the bottom source/drain region.

13. The method of claim 10 , wherein a top source/drain region is formed on the epitaxial layer after the air-gap spacer is defined.

14. The method of claim 10 , wherein a high-k metal gate (HKMG) stack is formed adjacent the fin.

15. The method of claim 10 , wherein an inter-level dielectric (ILD) oxide is deposited adjacent the hard mask.

16. The method of claim 10 , wherein the SiN is deposited with the recess created by the etching of the hard mask.

17. A semiconductor structure, comprising:
a fin formed over a bottom source/drain region;
a high-k metal gate (HKMG) stack formed adjacent the fin;
an epitaxial layer formed on the fin, the epitaxial layer having a thickness greeter than a thickness of the fin to define at least one gap region adjacent the fin; and
a top source/drain region formed on the epitaxial layer and over the at least one gap region.

18. The structure of claim 17 , wherein a hard mask is deposited before the epitaxial layer to cover the fin and the HKMG stack.

19. The structure of claim 18 , wherein the hard mask is etched to expose a top region of the fin to receive the epitaxial layer.

20. The structure of claim 19 , wherein the at least one gap region is defined adjacent top sidewalls of the fin.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Xie Ruilong
• Yamashita Tenko
• Yeh Chun-Chen

Classifications

• H01L29/4991 Primary

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/435

  Electricity · mapped topic

• H01L21/7682

  Electricity · mapped topic