Semiconductor device with low-K spacers

Patent metadata

Field	Value
Publication number	US-9425280-B2
Application number	US-201514711196-A
Country	US
Kind code	B2
Filing date	May 13, 2015
Priority date	Oct 22, 2012
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer.

First claim

What is claimed:

1. A device, comprising:
a gate structure positioned above an active region defined in a semiconducting substrate, said gate structure comprising a gate insulation layer and a gate electrode, said gate insulation layer having two upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate;
a first layer of insulating material positioned above and covering at least a portion of said active region;
a second layer of insulating material positioned above and covering at least a portion of said first layer of insulating material;
a third layer of insulating material positioned above and covering at least a portion of said second layer of insulating material; and
a low-k sidewall spacer positioned adjacent each of said vertically oriented upstanding portions of said gate insulation layer, wherein said low-k sidewall spacer contacts each of said first, second, and third layers of insulating material, wherein a portion of said low-k sidewall spacer extends into a recess that is positioned between said third layer of insulating material and said active region, said portion of said low-k sidewall spacer contacting a sidewall portion of said second layer of insulating material.

2. The device of claim 1 , wherein said low-k sidewall spacer is comprised of a material having a k value of less than 7.

3. The device of claim 1 , wherein said low-k sidewall spacer is positioned adjacent and contacts each of said vertically oriented upstanding portions of said gate insulation layer.

4. The device of claim 1 , further comprising a void formed in said low-k sidewall spacer.

5. The device of claim 1 , wherein said gate insulation layer is comprised of a high-k insulating material and said gate electrode is comprised of at least one layer of metal.

6. The device of claim 1 , further comprising a fourth layer of insulating material positioned above and covering at least a portion of said third layer of insulating material, wherein said low-k sidewall spacer contacts said fourth layer of insulating material.

7. The device of claim 6 , further comprising a gate cap layer positioned above and covering an upper surface of said gate structure, wherein an upper surface of said gate cap layer is substantially coplanar with an upper surface of said fourth layer of insulating material.

8. The device of claim 6 , wherein said low-k sidewall spacer contacts an upper surface of said first layer of insulating material and a sidewall surface of each of said second, third, and fourth layers of insulating material.

9. A device, comprising:
a gate structure positioned above an active region defined in a semiconducting substrate, said gate structure comprising a gate insulation layer and a gate electrode, said gate insulation layer having two upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate;
a first layer of insulating material positioned above a portion of said active region;
a second layer of insulating material positioned above a portion of said active region;
a third layer of insulating material positioned above said second layer of insulating material; and
a low-k sidewall spacer that is positioned adjacent to and contacts each of said vertically oriented upstanding portions of said gate insulation layer, wherein said low-k sidewall spacer is positioned above and covers a portion of an upper surface of said first layer of insulating material and wherein said low-k sidewall spacer is positioned laterally adjacent to and covers a portion of a sidewall surface of each of said second and third layers of insulating material.

10. The device of claim 9 , further comprising a void formed in said low-k sidewall spacer.

11. The device of claim 9 , wherein a portion of said low-k sidewall spacer extends into a recess that is positioned below said third layer of insulating material, above said active region, and between said second layer of insulating material and said gate electrode structure.

12. The device of claim 11 , wherein said gate insulation layer is comprised of a high-k insulating material and said gate electrode is comprised of at least one layer of metal.

13. The device of claim 9 , wherein said low-k sidewall spacer is comprised of a material having a k value of less than 7.

14. A device, comprising:
a gate structure positioned above an active region defined in a semiconducting substrate, said gate structure comprising a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal, said gate insulation layer having two upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate;
a low-k sidewall spacer that is positioned adjacent to and contacts each of said vertically oriented upstanding portions of said gate insulation layer, wherein said low-k sidewall spacer is comprised of a material having a k value of less than 7;
a void positioned within said low-k sidewall spacer;
a first layer of insulating material positioned above said semiconducting substrate and covering at least a portion of an upper surface of said active region;
a second layer of insulating material positioned above said semiconducting substrate and covering at least a portion of an upper surface of said first layer of insulating material;
a third layer of insulating material positioned above and covering at least a portion of an upper surface of said second layer of insulating material; and
a fourth layer of insulating material positioned above and covering at least a portion of an upper surface of said third layer of insulating material, wherein said low-k sidewall spacer contacts an upper surface of said first layer of insulating material and a sidewall surface of each of said second, third, and fourth layers of insulating material.

15. The device of claim 14 , further comprising raised source/drain regions, wherein at least a portion of said second layer of insulating material is positioned above and covers at least a portion of said raised source drain regions.

16. The device of claim 15 , wherein a portion of said low-k sidewall spacer is positioned in a recess that is defined by an upper surface of said raised source/drain regions, said sidewall surface of said second layer of insulating material, and a lower surface of said third layer of insulating material.

17. The device of claim 16 , further comprising a gate cap layer positioned above and covering an upper surface of said gate structure, wherein an upper surface of said gate cap layer is substantially coplanar with an upper surface of said fourth layer of insulating material.

Assignees

• Globalfoundries Inc

Inventors

• Cai Xiuyu
• Xie Ruilong
• Zhang Xunyuan

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10D64/68

  characterised by the insulator, e.g. by the gate insulator · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title