Multi-phase source/drain/gate spacer-epi formation

Patent metadata

Field	Value
Publication number	US-9337306-B2
Application number	US-201414319462-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer.

First claim

What is claimed is:

1. A method for forming a device, the method comprising:
epitaxially growing a first portion of a source/drain in a source/drain region on a fin in a finned substrate;
forming, subsequent to the epitaxially growing of the first portion of the epitaxial source/drain, a secondary spacer in the source/drain region; and
forming a remainder portion of the epitaxial source/drain in the source/drain region,
wherein the secondary spacer separates the epitaxial source/drain from a gate stack region on the fin.

2. The method according to claim 1 , further comprising forming, a set of fins from a substrate to form the finned substrate.

3. The method according to claim 1 , further comprising:
forming, prior to the epitaxially growing of the first portion of the epitaxial source/drain, a first gate stack region and a second gate stack region on the finned substrate.

4. The method according to claim 3 , the forming of the first and second gate stack regions further comprising:
forming a dummy gate on the finned substrate in each of the first gate stack region and the second gate stack region; and
forming a primary spacer on a vertical surface of each dummy gate,
wherein the source/drain region is between the first gate stack region and the second gate stack region, and
wherein the secondary spacer is formed over the primary spacer on the vertical surface of each dummy gate.

5. The method according to claim 4 , wherein the secondary spacer restricts a growth of the epitaxial source/drain in a direction of an adjacent source/drain.

6. The method according to claim 4 , wherein the secondary spacer comprises a material that is different from a material of the primary spacer.

7. The method according to claim 1 ,
wherein the epitaxially growing of the first portion of the epitaxial source/drain further comprises growing a first epitaxial layer on the fin to a pre-determined intermediate size; and
wherein the forming of the remainder portion of the epitaxial source/drain further comprises growing a second epitaxial layer on the first epitaxial layer to a final size.

8. The method according to claim 1 , further comprising:
etching, prior to the epitaxially growing of the first portion of the epitaxial source/drain, a trench in the source/drain region; and
etching, subsequent to the forming of the secondary spacer and prior to the forming of the remainder portion of the source/drain, a trench in the first portion of the source/drain.

9. The method according to claim 4 , further comprising:
removing the dummy gate from the gate stack regions; and
forming a replacement metal gate in an opening in the gate stack regions resulting from the removing of the dummy gate.

10. A method for forming an epitaxial source/drain in a fin-shaped field effect transistor (FinFET) device, the method comprising:
etching a trench in a source/drain region of a fin of the FinFET device situated between a first gate stack region and a second gate stack region, each of the first gate stack region and the second gate stack region comprising a primary spacer along a vertical surface;
forming a first portion of the source/drain in the trench on the fin;
forming, subsequent to the forming of the first portion of the source/drain, a secondary spacer over the primary spacer on the vertical surface;
removing the secondary spacer from over the first portion of the source/drain; and
forming a remainder portion of the source/drain in a portion of the source/drain region adjacent to the secondary spacer.

11. The method according to claim 10 , further comprising forming a set of fins from a substrate to form a finned substrate.

12. The method according to claim 11 , further comprising:
forming, prior to the forming of the first portion of the source/drain, the first gate stack region and the second gate stack region on the finned substrate, wherein each of the first and second gate stack regions further comprise a dummy gate.

13. The method according to claim 10 , wherein the secondary spacer restricts a growth of the source/drain in a direction of an adjacent source/drain.

14. The method according to claim 10 ,
wherein the forming of the first portion of the source/drain further comprises growing a first epitaxial layer on the fin to a pre-determined intermediate size; and
wherein the forming of the remainder portion of the source/drain further comprises growing a second epitaxial layer on the first epitaxial layer to a final size.

15. The method according to claim 10 , wherein the secondary spacer comprises a material that is different from a material of the primary spacer.

16. The method according to claim 12 , further comprising:
removing the dummy gate from the gate stack regions; and
forming a replacement metal gate in an opening in the gate stack regions resulting from the removing of the dummy gate.

Assignees

• Globalfoundries Inc

Inventors

• Peng Jianwei
• Wu Xusheng
• Yu Hong
• Lun Zhao

Classifications

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title