Method for manufacturing vertically integrated semiconductor device

Patent metadata

Field	Value
Publication number	US-9911822-B2
Application number	US-201615336847-A
Country	US
Kind code	B2
Filing date	Oct 28, 2016
Priority date	Nov 25, 2014
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A vertically integrated semiconductor device in accordance with various embodiments may include: a first semiconducting layer; a second semiconducting layer disposed over the first semiconducting layer; a third semiconducting layer disposed over the second semiconducting layer; and an electrical bypass coupled between the first semiconducting layer and the second semiconducting layer.

First claim

What is claimed is:

1. A method of manufacturing a vertically integrated semiconductor device, the method comprising:
forming a second semiconducting layer over a first semiconducting layer;
forming a third semiconducting layer over the second semiconducting layer; and
forming an electrical short between the first and second semiconducting layers,
wherein forming the electrical short comprises:
forming at least one trench extending through the third and second semiconductor layers and partially through the first semiconductor layer;
providing an electrically insulating material in the at least one trench covering the sidewalls of the third semiconductor layer and partially covering the sidewalls of the second semiconductor layer; and
depositing electrically conductive material into the at least one trench, wherein the electrically conductive material completely fills the at least one trench and wherein the electrically conductive material in the at least one trench provides the electrical short between the first and second semiconducting layers and wherein the electrically insulating material in the at least one trench is disposed so that the electrically conductive material in the at least one trench does not provide an electrical short between the second and third semiconductor layers.

2. The method of claim 1 , wherein forming the at least one trench comprises:
forming a patterned mask layer over the third semiconductor layer, the patterned mask defining a position of the at least one trench, and
etching to remove material from the first, second, and third semiconductor layers.

3. The method of claim 1 , wherein the first and second semiconducting layers are oppositely doped semiconducting layers forming a pn-junction.

4. The method of claim 1 , wherein the electrically conductive material has a specific electrical resistivity of less than or equal to 1 mΩ·cm.

5. The method of claim 1 , wherein the electrically insulating material comprises dopant source material.

6. The method of claim 1 , wherein the electrically insulating material comprises borophosphosilicate glass.

7. The method of claim 1 , wherein the electrically insulating material comprises an oxide layer.

8. The method of claim 1 , wherein forming the electrical short further comprises:
forming a first portion of the at least one trench extending through the third semiconductor layer and partially through the second semiconductor layer;
providing the electrically insulating material in the first portion of the at least one trench covering the sidewalls of the third semiconductor layer and partially covering the sidewalls of the second semiconductor layer; and
forming a second portion of the at least one trench extending through the remainder of the second semiconductor layer and partially through the first semiconductor layer.

9. The method of claim 1 , wherein providing the electrically insulating material into the at least one trench comprises performing a conformal deposition process.

10. The method of claim 9 , wherein the conformal deposition process deposits the electrically insulating material only on one or more sidewalls of the trench.

11. The method of claim 9 , wherein the conformal deposition process comprises plating process, an atomic layer deposition (ALD) process, or a chemical vapor deposition (CVD) process.

12. A method for manufacturing a semiconductor device, the method comprising:
providing a carrier;
forming a trench from a surface of the carrier into the carrier, the trench bridging a buried pn-junction disposed within the carrier;
providing a buried pn-short in the trench, the buried pn-short electrically bypassing the buried pn-junction;
covering the buried pn-short with an insulating layer; and,
providing one or more electrical connections to the carrier.

13. The method of claim 12 , wherein the buried pn-junction is a first buried pn-junction, and wherein the carrier further comprises a second buried pn-junction.

14. The method of claim 13 , wherein the carrier comprises an isolation trench, wherein the isolation trench electrically separates the second buried pn-junction from the buried pn-short so that the second pn-junction is not electrically bypassed by the buried pn-short.

15. The method of claim 12 ,
wherein the carrier comprises a semiconductor wafer and wherein forming the trench comprises:
depositing an electrically insulating layer over a front side of the wafer,
patterning the electrically insulating layer, and
etching the trench into the wafer from the front side of the wafer.

16. The method of claim 15 , wherein providing the buried pn-short comprises:
depositing a metal over the front side of the wafer, wherein depositing the metal over the front side of the wafer at least partially fills the trench with the metal, and
removing deposited metal from the entire front side of the wafer, wherein the metal in the trench remains.

17. The method of claim 16 , further comprising:
after providing the buried pn-short and before providing electrical connections:
depositing an insulating layer on the front side of the carrier, the insulating layer covering the metal remaining in the trench, and
planarizing the carrier from the front side.

18. The method of claim 15 , wherein the electrically insulating layer is an oxide layer.

Assignees

• Infineon Technologies Ag

Inventors

• Schmenn Andre
• Sojka Damian

Classifications

• H10P14/432

  using selective deposition · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H01L21/28562

  Electricity · mapped topic

• H01L29/66371 Primary

  Electricity · mapped topic

• H01L29/7412

  Electricity · mapped topic