Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)

Patent metadata

Field	Value
Publication number	US-9793256-B2
Application number	US-201514627750-A
Country	US
Kind code	B2
Filing date	Feb 20, 2015
Priority date	Nov 30, 2006
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.

First claim

I claim:

1. A method for manufacturing a transient voltage suppressing (TVS) device comprising:
a) growing a first lightly doped epitaxial layer of a first conductivity type on top of a heavily doped substrate of the first conductivity type followed by applying a first implant mask to implant a buried region of a second conductivity type followed by applying a second implanting mask to form a deep voltage breakdown (VBD) trigger implant layer of the first conductivity type underneath the buried region;
b) growing a second epitaxial layer of the first conductivity type on top of the first epitaxial layer followed by applying a trench mask to open isolation trenches and filling the isolation trenches with an insulation material to separate the first and second epitaxial layers of the first conductivity type into at least two mutually isolated first epitaxial region and a second epitaxial region wherein the first epitaxial region encompasses the buried region of the second conductivity type and the deep VBD trigger implant layer; and
c) applying a third implant mask to implant a first top source region in the first epitaxial region and a second top source region in the second epitaxial region wherein the second epitaxial layer in the first epitaxial region interfacing with the buried region of the second conductivity type forming a high-side steering diode of the TVS device on top of a Zener diode formed between the buried region of the second conductivity type interfacing the first epitaxial layer of the first conductivity type; and wherein the top source region of the second conductivity type in the second epitaxial region interfaced with the second epitaxial layer of the first conductivity type forming a low-side steering diode of the TVS device.

2. The method of claim 1 further comprising:
forming a top insulation layer on top of the second epitaxial layer and opening a plurality of contact openings followed by forming and patterning a metal contact layer on top of the top insulation layer with a first input/output (I/O) pad to contact the high-side steering diode through a first contact opening that is opened on top of the second epitaxial layer in the first epitaxial region next to the Zener diode of the TVS device.

3. The method of claim 2 further comprising a step of:
patterning the top metal contact layer into a second I/O pad to contact the second top source region of the low-side steering diode through a second contact opening that is opened on top of the second epitaxial layer in the second epitaxial region.

4. The method of claim 2 further comprising:
patterning the top metal contact layer into a Vcc pad to contact the first top source region of the Zener diode through a third contact opening that is opened on top of the first top source region in the first epitaxial region.

5. The method of claim 2 further comprising:
implanting a heavily doped contact region of the first conductivity type in the second epitaxial layer underneath the first contact opening for improving an electric contact between the first I/O pad and the high-side steering diode of the TVS device.

6. The method of claim 1 wherein:
said step of applying the second implanting mask to form the deep voltage breakdown (VBD) trigger implant layer of the first conductivity type underneath the buried region is a step of forming the deep VBD trigger implant layer at a lateral distance away from the high-side steering diode in the first epitaxial layer.

7. The method of claim 1 wherein:
said step of applying the second implanting mask to form the deep voltage breakdown (VBD) trigger implant layer of the first conductivity type underneath the buried region is a step of forming the deep VBD trigger implant layer as two separate layer segments underneath the buried region of the second conductivity type with a gap vertically underneath the high-side steering diode in the first epitaxial layer.

8. The method of claim 1 wherein:
the step of applying a third implant mask to implant the first top source region in the first epitaxial region and the second top source region in the second epitaxial region is a step of implanting the first and second top source regions as a first and second top N-type source regions in the first and second P-type epitaxial layers.

9. The method of claim 1 wherein:
the step of isolation and separating the first and second epitaxial regions further comprising a step of opening an additional isolation trench to form an intermediate epitaxial region disposed between the first epitaxial region and second epitaxial region to further separate the high-side steering diode formed in the first epitaxial region from the low-side steering diode formed in the second epitaxial region.

10. The method of claim 1 wherein:
the step of applying a third implant mask to implant a first top source region in the first epitaxial region and a second top source region in the second epitaxial region further comprising a step of implanting the first top source region having a greater area than the second top source region to form the Zener diode to occupy a greater area than the high-side and the low-side steering diodes.

11. The method of claim 1 wherein:
the step of applying a third implant mask to implant a first top source region in the first epitaxial region and a second top source region in the second epitaxial region further comprising a step of implanting the first top source region in a center area on top of the second epitaxial layer and occupying a greater area than the second top source region whereby the Zener diode is formed to occupy the center area and having the greater area than the high-side and the low-side steering diodes.

12. The method of claim 1 further comprising:
forming backside metal below the bottom surface of the substrate to function as a ground terminal for the TVS device.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Bobde Madhur

Classifications

• H10P30/22

  using masks · CPC title

• H01L29/66371

  Electricity · mapped topic

• H01L21/266

  Electricity · mapped topic

• H01L29/66106

  Electricity · mapped topic

• H01L29/7412

  Electricity · mapped topic