Methods for an ESD protection circuit including trigger-voltage tunable cascode transistors

Patent metadata

Field	Value
Publication number	US-10147715-B2
Application number	US-201715481202-A
Country	US
Kind code	B2
Filing date	Apr 6, 2017
Priority date	Jul 20, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

First claim

What is claimed is:

1. A method comprising:
providing a p-type substrate including adjacent n-well areas, over the substrate, each pair of n-well areas separated by a p-well area;
providing p-type and n-type junction areas in the n-type well areas;
providing p-type or p-type and n-type junction areas in the p-type well areas;
forming isolation trench regions separating the n-type and p-type well areas;
forming fins, spaced from each other, perpendicular to and over the n-type and p-type junction areas;
forming junction-type devices by forming electrical connections between the n-type and p-type junction areas in the n-type well areas and the substrate, wherein a first-stage junction-type device in an n-type well area includes stacked n-type and p-type junction areas, and wherein the first-stage junction-type device is adjacent a p-type well area including n-type and p-type junction areas; and
connecting the junction areas in the p-type well areas to an electrical ground.

2. The method according to claim 1 , wherein:
the p-type well area adjacent the first-stage junction-type device includes multi p-type junction areas.

3. The method according to claim 1 , comprising:
setting a spacing between the n-type and p-type junction areas and between adjacent p-type junction areas based on a target trigger-voltage.

4. The method according to claim 1 , wherein:
the junction type devices include a pn-type diode.

5. The method according to claim 1 , comprising:
connecting the junction areas in the n-type well areas to an electrical ground.

Assignees

• Globalfoundries Inc

Inventors

• Lee Chien-Hsin
• Natarajan Mahadeva Iyer
• Prabhu Manjunatha

Classifications

• H10D84/01 Primary

  Manufacture or treatment · CPC title

• H01L21/823431

  Electricity · mapped topic

• H01L29/7408

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L27/0259

  Electricity · mapped topic