ESD protection structure

Patent metadata

Field	Value
Publication number	US-9893050-B2
Application number	US-201514953711-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Jun 30, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

An ESD protection structure comprising a thyristor structure. The thyristor structure is formed from a first P-doped section comprising a first P-doped well formed within a first region of a P-doped epitaxial layer, a first N-doped section comprising a deep N-well structure, a second P-doped section comprising a second P-doped well formed within a second region of the epitaxial layer, and a second N-doped section comprising an N-doped contact region formed within a surface of the second P-doped well. The ESD protection structure further comprises a P-doped region formed on an upper surface of the deep N-well structure and forming a part of the second P-doped section of the thyristor structure.

First claim

We claim:

1. An electrostatic discharge, ESD, protection structure formed within a semiconductor substrate of an integrated circuit device, the ESD protection structure comprising:
at least a first thyristor structure being formed from
a first P-doped section comprising a first P-doped well formed within a first region of a P-doped epitaxial layer, wherein the first P-doped section is coupled to a power supply contact of the integrated circuit device to which ESD currents are to be shunted,
a first N-doped section comprising a deep N-well structure,
a second P-doped section comprising a second P-doped well formed within a second region of the epitaxial layer, and
a second N-doped section comprising an N-doped contact region formed within a surface of the second P-doped well, the second N-doped section coupled to a contact of the integrated circuit device; and

a P-doped region formed on an upper surface of the deep N-well structure in contact with the second P-doped region of the epitaxial layer such that the P-doped region formed on the upper surface of the deep N-well structure forms a part of the second P-doped section of the first thyristor structure.

2. The ESD protection structure of claim 1 further comprising an isolation region formed on the upper surface of the deep N-well structure and arranged to isolate the P-doped region formed on the upper surface of the deep-N-well structure from the first P-doped section of the first thyristor structure.

3. The ESD protection structure of claim 2 , wherein the isolation region comprises a shallow trench isolation region.

4. The ESD protection structure of claim 1 , wherein the P-doped region formed on the upper surface of the deep N-well structure comprises a high dopant concentration.

5. The ESD protection structure of claim 1 further comprising an N-doped buried layer formed to vertically isolate at least the second region of the epitaxial layer.

6. The ESD protection structure of claim 1 formed within an isolation trench recessed within the semiconductor substrate of the integrated circuit device.

7. The ESD protection structure of claim 1 further comprising:
a second thyristor structure being formed from
a first P-doped section comprising the second P-doped well formed within the second region of the P-doped epitaxial layer, wherein the first P-doped section is coupled to the contact of the integrated circuit device,
a first N-doped section comprising the deep N-well structure,
a second P-doped section comprising the first P-doped well formed within the first region of the epitaxial layer, and
a second N-doped section comprising an N-doped contact region formed within a surface of the first P-doped well, the second N-doped section coupled to the power supply contact of the integrated circuit device to which ESD currents are to be shunted.

8. An integrated circuit device comprising:
at least one semiconductor substrate comprising at least one electrostatic discharge, ESD, protection structure, wherein the ESD protection structure comprises at least a first thyristor structure being formed from
a first P-doped section comprising a first P-doped well formed within a first region of a P-doped epitaxial layer wherein the first P-doped section is coupled to a power supply contact of the integrated circuit device to which ESD currents are to be shunted,
a first N-doped section comprising a deep N-well structure,
a second P-doped section comprising a second P-doped well formed within a second region of the epitaxial layer, and
a second N-doped section comprising an N-doped contact region formed within a surface of the second P-doped well, the second N-doped section coupled to a contact of the integrated circuit device;

wherein the ESD protection structure further comprises a P-doped region formed on an upper surface of the deep N-well structure in contact with the second P-doped region of the epitaxial layer such that the P-doped region formed on the upper surface of the deep N-well structure forms a part of the second P-doped section of the first thyristor structure.

9. The integrated circuit device of claim 8 , wherein the ESD protection structure further comprises an isolation region formed on the upper surface of the deep N-well structure and arranged to isolate the P-doped region formed on the upper surface of the deep-N-well structure from the first P-doped section of the first thyristor structure.

10. The integrated circuit device of claim 9 , wherein the isolation region comprises a shallow trench isolation region.

11. The integrated circuit device of claim 8 , wherein the P-doped region formed on the upper surface of the deep N-well structure comprises a high dopant concentration.

12. The integrated circuit device of claim 8 , wherein the ESD protection structure further comprises an N-doped buried layer formed to vertically isolate at least the second region of the epitaxial layer.

13. The integrated circuit device of claim 8 , wherein the ESD protection structure is formed within an isolation trench recessed within the semiconductor substrate of the integrated circuit device.

14. The integrated circuit device of claim 8 , wherein the ESD protection structure further comprising:
a second thyristor structure being formed from
a first P-doped section comprising the second P-doped well formed within the second region of the P-doped epitaxial layer wherein the first P-doped section coupled to the contact of the integrated circuit device,
a first N-doped section comprising the deep N-well structure,
a second P-doped section comprising the first P-doped well formed within the first region of the epitaxial layer, and
a second N-doped section comprising an N-doped contact region formed within a surface of the first P-doped well, the second N-doped section coupled to the power supply contact of the integrated circuit device to which ESD currents are to be shunted.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Laine Jean Philippe
• Besse Patrice

Classifications

• H01L29/7416

  Electricity · mapped topic

• H01L27/0255 Primary

  Electricity · mapped topic

• H01L29/66371

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H10D89/713 Primary

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title