ESD protection structure and method of fabrication thereof

Patent metadata

Field	Value
Publication number	US-9960251-B2
Application number	US-201514829961-A
Country	US
Kind code	B2
Filing date	Aug 19, 2015
Priority date	Mar 19, 2015
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

An ESD protection structure comprising a first semiconductor region of a first doping type, a second semiconductor region of the first doping type, a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the first and second semiconductor regions of the first doping type, and a first contact region of the second doping type formed within a surface of the second semiconductor region. A thyristor structure is formed within the ESD protection structure comprising the first contact region of the second doping type, the second semiconductor region of the first doping type, the semiconductor structure of the second doping type, and the first semiconductor region of the first doping type. Wherein no contact region is formed within a surface of the semiconductor structure of the second doping type between the first and second semiconductor regions of the first doping type.

First claim

We claim:

1. An electrostatic discharge, ESD, protection structure formed within a semiconductor substrate of an integrated circuit device; the ESD protection structure comprising:
a first semiconductor region of a first doping type;
a second semiconductor region of the first doping type;
a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the first and second semiconductor regions of the first doping type; and
a first contact region of the second doping type formed within a surface of the second semiconductor region of the first doping type, the surface of the second semiconductor region of the first doping type being co-planar with a surface of the semiconductor substrate;
a thyristor structure is formed within the ESD protection structure comprising at least:
the first contact region of the second doping type,
the second semiconductor region of the first doping type containing the first contact region,
the semiconductor structure of the second doping type, and the first semiconductor region of the first doping type; and

wherein no contact region is formed within a surface of the semiconductor structure of the second doping type and no contact region is formed within a surface of the semiconductor structure of the second doping type between the first and second semiconductor regions of the first doping type, said surface of the semiconductor structure of the second doping type being co-planar with the surface of the semiconductor substrate.

2. The ESD protection structure of claim 1 , further comprising a shallow trench isolation layer formed over the surface of the semiconductor structure of the second doping type between the first and second semiconductor regions of the first doping type.

3. The ESD protection structure of claim 1 , further comprising at least one further contact region of the first doping type formed within a surface of the second semiconductor region of the first doping type, said surface of the second semiconductor region of the first doping type being co-planar with the surface of the semiconductor substrate.

4. The ESD protection structure of claim 3 further comprising a metalized contact layer formed over a contact surface of each of the first and at least one further contact regions.

5. The ESD protection structure of claim 1 , wherein the first and second semiconductor regions of the first doping type are formed within an epitaxial layer within the semiconductor substrate.

6. The ESD protection structure of claim 1 , further comprising doped wells of the first doping type formed within the surfaces of the first and second semiconductor regions of the first doping type, and the first contact region of the second doping type is formed within a surface of a doped well within the second semiconductor region of the first doping type, said surface of the doped well being co-planar with the surface of the semiconductor substrate.

7. The ESD protection structure of claim 1 , further comprising a buried layer of the second doping type formed to isolate the first semiconductor region of the first doping type from a floor of an isolation trench within which the ESD protection structure is contained, whilst permitting contact between the second semiconductor region of the first doping type and the floor of the isolation trench.

8. An integrated circuit device comprising a semiconductor substrate comprising at least one electrostatic discharge, ESD, protection structure formed within the semiconductor substrate; the at least one ESD protection structure comprising:
a first semiconductor region of a first doping type;
a second semiconductor region of the first doping type;
a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the first and second semiconductor regions of the first doping type; and
a first contact region of the second doping type formed within a surface of the second semiconductor region of the first doping type, the surface of the second semiconductor region of the first doping type being co-planar with a surface of the semiconductor substrate;
a thyristor structure is formed within the ESD protection structure comprising at least:
the first contact region of the second doping type,
the second semiconductor region of the first doping type containing the first contact region,
the semiconductor structure of the second doping type, and
the first semiconductor region of the first doping type; and

wherein no contact region is formed within a surface of the semiconductor structure of the second doping type and no contact region is formed within a surface of the semiconductor structure of the second doping type between the first and second semiconductor regions of the first doping type, said surface of the semiconductor structure of the second doping type being co-planar with the surface of the semiconductor substrate.

9. The ESD protection structure of claim 8 , further comprising a shallow trench isolation layer formed over the surface of the semiconductor structure of the second doping type between the first and second semiconductor regions of the first doping type.

10. The ESD protection structure of claim 8 , further comprising at least one further contact region of the first doping type formed within a surface of the second semiconductor region of the first doping type, said surface of the second semiconductor region of the first doping type being co-planar with the surface of the semiconductor substrate.

11. The ESD protection structure of claim 10 , further comprising a metalized contact layer formed over a contact surface of each of the first and at least one further contact regions.

12. The ESD protection structure of claim 8 , wherein the first and second semiconductor regions of the first doping type are formed within an epitaxial layer within the semiconductor substrate.

13. The ESD protection structure of claim 8 , further comprising doped wells of the first doping type formed within the surfaces of the first and second semiconductor regions of the first doping type, and the first contact region of the second doping type is formed within a surface of a doped well within the second semiconductor region of the first doping type, said surface of the doped well being co-planar with the surface of the semiconductor substrate.

14. The ESD protectionstructure of claim 8 , further comprising a buried layer of the second doping type formed to isolate the first semiconductor region of the first doping type from a floor of an isolation trench within which the ESD protection structure is contained, whilst permitting contact between the second semiconductor region of the first doping type and the floor of the isolation trench.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Laine Jean Philippe
• Besse Patrice

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title