Top electrode dome formation

Patent metadata

Field	Value
Publication number	US-9905282-B1
Application number	US-201715608407-A
Country	US
Kind code	B1
Filing date	May 30, 2017
Priority date	May 30, 2017
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Methods of fabricating a dome-shaped MTJ TE and the resulting devices are provided. Embodiments include forming a MRAM stack having a laterally separated MTJ structures and the MRAM and a logic stack each having a SiN layer; forming first trenches through the MRAM stack to a portion of the SiN layer above an MTJ structure; forming second trenches through the SiN layer fully landing on an upper portion of the MTJ structures and removing the SiN layer of the logic stack; forming a TaN layer over the MRAM and logic stack; removing portions of the TaN layer on opposite sides of the MTJ structures and therebetween; forming an oxide layer over the MRAM and logic stacks; and forming vias through the oxide layer of the MRAM stack down the TaN layer above MTJ structures and a via through the logic stack.

First claim

What is claimed is:

1. A method comprising:
forming a magnetic random access memory (MRAM) stack and a logic stack of an integrated circuit (IC) structure, the MRAM stack having a laterally separated magnetic tunnel junction (MTJ) structures and the MRAM and logic stacks each having a silicon nitride (SiN) layer;
forming first trenches through the MRAM stack down through a portion of the SiN layer, each first trench formed above an MTJ structure;
forming second trenches through the SiN layer of the MRAM stack, the second trenches fully landed on an upper portion of the MTJ structures and the formation removing the SiN layer of the logic stack;
forming a tantalum nitride (TaN) layer over the MRAM and logic stacks;
removing portions of the TaN layer on opposite sides of the MTJ structures and therebetween;
forming an oxide layer over the MRAM and logic stacks; and
forming vias through the oxide layer of the MRAM stack down the TaN layer above each MTJ structure and a via through the logic stack.

2. A method according to claim 1 , comprising forming the MRAM and logic stacks by:
forming the passivation layer over an interlayer dielectric (ILD) of the IC structure;
forming a trench through the passivation layer down to the ILD, the trench forming a MRAM region and a logic region;
forming a first oxide layer over the passivation layer;
forming lower interconnect structures laterally separated through the first oxide and passivation layers of the MRAM region;
forming a MTJ layer over the first oxide layer of the MRAM region and the lower interconnect structures;
etching the MTJ layer down to the first oxide layer and lower interconnect structures, the etching forming a MTJ structure over a center portion of each lower interconnect;
forming the SiN layer over the first oxide layer and the MTJ structures;
forming a second oxide layer over the SiN layer;
forming a near-frictionless carbon (NFC) layer over the second oxide layer;
forming a low temperature oxide (LTO) layer over the NFC layer; and
forming a photoresist layer over the LTO.

3. A method according to claim 2 , comprising forming the SiN layer to a thickness of 10 nanometer (nm) to 40 nm.

4. A method according to claim 2 , comprising forming the first trenches by:
forming a trench with a bottom critical dimension (CD) of 50 nm to 110 nm through the photoresist layer above each MTJ structure; and
etching the LTO, NFC, second oxide, and a portion of the SiN layers through each trench.

5. A method according to claim 2 , comprising forming the second trenches by:
stripping the photoresist, LTO, and NFC layers; and
etching the SiN layer until each second trench has a bottom CD of 30 nm to 90 nm, the etching removing the second oxide layer from the logic stack.

6. A method according to claim 5 , wherein the etching of the SiN layer comprises a fully-landed etch process or a chemical vapor deposition (CVD) film deposition and etch process.

7. A method according to claim 2 , comprising forming each dome-shaped TaN layer by:
forming the TaN layer to a thickness of 10 nm to 40 nm over the MRAM and logic stacks; and
etching portions of the TaN layer down to the second oxide layer on opposite sides of each MTJ structure and therebetween with lithography, and consecutively removing the TaN layer from over the logic stack.

8. A method according to claim 1 , further comprising dielectric deposition, planarization and interconnect formation in both the MRAM and logic regions.

9. A device comprising:
a passivation layer over an interlayer dielectric (ILD) of a magnetic random access memory (MRAM) region and a logic region of an integrated circuit (IC) structure, the MRAM and logic regions laterally separated;
a first oxide layer over the passivation layer;
lower interconnect structures laterally separated through the first oxide and passivation layers of the MRAM region;
magnetic tunnel junction (MTJ) structures laterally separated, each MTJ structure over a center portion of a lower interconnect;
silicon nitride (SiN) spacers formed around each MTJ structure;
a domed-shaped tantalum nitride (TaN) layer over each MTJ structure, the domed-shaped TaN layers laterally separated;
a second oxide layer over the MRAM and logic regions;
a via through the second oxide layer down to the domed-shaped TaN layer over each MTJ structure; and
a via through the logic region down to the ILD.

10. A device according to claim 9 , wherein the TaN layer comprises a thickness of 10 nanometer (nm) to 40 nm.

11. A device according to claim 9 , wherein the second oxide layer comprises a thickness of 30 nm to 90 nm.

12. A device according to claim 11 , wherein each SiN spacer comprises a horizontal portion over the first oxide layer and a portion of a lower interconnect structure and the portions over the first oxide layer between the MTJ structures are contiguous.

13. A device according to claim 11 , wherein each SiN spacer comprises a thickness of 10 nm to 40 nm.

14. A device according to claim 11 , wherein each domed-shaped TaN layer has an upper critical dimension (CD) of 60 nm to 150 nm.

15. A device according to claim 11 , wherein a contact area between each domed-shaped TaN layer and the MTJ structure has a CD of 30 nm to 90 nm.

16. A device according to claim 9 , wherein each SiN spacer has a lower portion with a width of 10 nm to 40 nm and a tapered upper portion.

17. A method comprising:
forming a magnetic random access memory (MRAM) stack and a logic stack of an integrated circuit (IC) structure, the MRAM stack having magnetic tunnel junction (MTJ) structures and the MRAM and logic stacks each having a silicon nitride (SiN) layer;
etching the SiN layer of the logic stack and portions of the SiN layer of the MRAM stack, the etching forming SiN spacers around each MTJ structure;
forming a conformal tantalum nitride (TaN) layer over the MRAM and logic stacks;
removing the TaN layer over the logic stack and portions of the TaN layer between the MTJ structures and leaving the TaN layer covering the MTJ structures un-etched;
forming an oxide layer over the MRAM and logic regions;
forming a via through the oxide layer down to the TaN layer above each MTJ structure and through the logic stack; and
planarizing the oxide layer prior to forming a metal contact layer over the MRAM and logic stacks.

18. A method according to claim 17 , comprising forming the MRAM and logic stacks by:
forming a passivation layer over an interlayer dielectric (ILD) on the IC structure;
forming a trench through the passivation layer down to the ILD, the trench forming a MRAM region and a logic region;
forming a first oxide layer over the passivation layer;
forming a lower interconnect structures laterally separated through the first oxide and passivation layers of the MRAM region;
forming a MTJ layer over the lower interconnect structures and the first oxide layer of the MRAM region;
etching the MTJ layer down to the first oxide layer and lower interconnect structures, the etching forming a MTJ structure over a center portion of each lower interconnect; and
forming the SiN layer over the first oxide layer and the MTJ structures.

19. A method according to claim 17 , comprising forming the SiN layer to a thickness of 10 nanometer (nm) to 40 nm.

20. A method according to claim 17 , comprising forming the TaN layer to a thickness of 10 nm to 40 nm.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Yi Wanbing
• Hsieh Curtis Chun I
• Siah Soh Yun
• Tan Juan Boon

Classifications

• H01F41/303

  with exchange coupling adjustment of magnetic film pairs, e.g. interface modifications by reduction, oxidation · CPC title

• H01F10/3254

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

• G11C11/16 Primary

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• H01L43/12

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic