Integrated magnetic random access memory with logic device

Patent metadata

Field	Value
Publication number	US-2016351797-A1
Application number	US-201615164914-A
Country	US
Kind code	A1
Filing date	May 26, 2016
Priority date	May 27, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.

First claim

What is claimed is:

1 . A method of forming a device comprising:
providing a substrate defined with at least first and second regions; providing a first dielectric layer over the first and second regions of the substrate, wherein the first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions; providing a first interlevel dielectric (ILD) layer over the first dielectric layer, wherein the first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region; and forming a magnetic random access memory (MRAM) cell in the second region, the MRAM cell comprises a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.

2 . The method of claim 1 wherein the substrate further comprises a third region, and wherein the first region is a logic region for accommodating at least one logic component, the second region is a memory cell region for accommodating the MRAM cell and the third region is a scribe lane of the device.

3 . The method of claim 1 comprising processing the first dielectric layer to form a plurality of via openings in the first and second regions, wherein the via openings extend from a top surface of the first dielectric layer to a top surface of the substrate.

4 . The method of claim 3 comprising partially filling the via openings with a conductive material to form the contact plugs while leaving recesses over a top portion of the via openings in the first and second regions.

5 . The method of claim 4 comprising:
providing a bottom electrode layer over the first dielectric layer and fills the recesses; and
performing a planarization process to remove excess bottom electrode layer to define the bottom electrode in the first and second regions.

6 . The method of claim 5 comprising:
patterning the first dielectric layer to form an alignment trench in a third region defined on the substrate;
forming various layers of MTJ stack of the MTJ element over the first, second and third regions, wherein the various layers of the MTJ stack track profile of the alignment trench in the third region to form a topography feature; and
patterning the various layers of the MTJ stack using topography feature which is visible from top surface of the various layers of the MTJ stack to align the patterned MTJ stack to the bottom electrode.

7 . The method of claim 6 comprising forming a dielectric liner over first, second and third regions, wherein the dielectric liner covers the top surface of the first dielectric layer and exposed surfaces of the MTJ stack in the second region.

8 . The method of claim 1 comprising processing the first ILD layer to form dual damascene openings having a trench and a via opening in the first region and to form a damascene opening having a trench in the second region.

9 . The method of claim 8 comprising filling the trench and via opening with a conductive to form the metal line in M1 level and via contact in V0 level in the first region and filling the trench with the conductive material to form the metal line in M1 level in the second region.

10 . The method of claim 9 wherein the metal line in M1 level in the second region is directly coupled to the MTJ element.

11 . The method of claim 9 wherein the MTJ element in the second region is formed in the V0 level of the first ILD layer.

12 . A device comprising:
a substrate defined with at least first and second regions; a first dielectric layer disposed over the first and second regions of the substrate, wherein the first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions; a first interlevel dielectric (ILD) layer disposed over the first dielectric layer, wherein the first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region; and a magnetic random access memory (MRAM) cell disposed in the second region, wherein the MRAM cell comprises a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.

13 . The device of claim 12 wherein the first region is a logic region for accommodating at least one logic component and the second region is a memory cell region for accommodating the MRAM cell.

14 . The device of claim 13 comprising logic transistors disposed in the logic region and select transistors disposed in the second region, wherein the contact plugs in the first dielectric layer are directly coupled to contact regions of the logic and select transistors.

15 . The device of claim 12 wherein the first dielectric layer comprises a plurality of via openings in the first and second regions, wherein the via openings extend from a top surface of the first dielectric layer to a top surface of the substrate.

16 . The device of claim 15 wherein the contact plugs partially fill the via openings while leaving recesses over a top portion of the via openings in the first and second regions.

17 . The device of claim 16 comprising bottom electrodes, wherein the bottom electrodes occupy the recesses in the first and second regions and comprise a top surface which is substantially coplanar with a top surface of the first dielectric layer.

18 . The device of claim 17 wherein the bottom electrode in the first region is coupled to the via contact in V0 level while the bottom electrode in the second region is coupled to the MTJ element.

19 . The device of claim 12 wherein the metal lines in M1 metal level in the first region are directly coupled to the via contact in V0 via level while the metal lines in M1 metal level in the second region are directly coupled to the MTJ elements.

20 . The device of claim 12 wherein the MTJ element in the second region is disposed in the V0 level of the first ILD layer.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Yi Wanbing
• Jiang Yi
• Wang Daxiang
• Shao Wei
• Tan Juan Boon

Classifications

• H01L43/02

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L43/08 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title