Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM) including a passivation layer formed along lateral sidewalls of a magnetic tunnel junction of the STT-MRAM

Patent metadata

Field	Value
Publication number	US-9349772-B2
Application number	US-201414261543-A
Country	US
Kind code	B2
Filing date	Apr 25, 2014
Priority date	Apr 25, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit comprising:
forming a trench within a passivation layer, the passivation layer being formed over an interlayer dielectric (ILD) layer and a metallization layer within the ILD layer, the trench being formed over at least a portion of the metallization layer;
depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, and a top electrode layer over the passivation layer and within the trench, thereby filling the trench, wherein the trench is filled with portions of the bottom electrode layer and portions of the MTJ layer, but is not filled with the top electrode layer;
removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing, wherein an entirety of the bottom electrode layer remains in place during and subsequent to the step of removing portions of the MTJ layer and the top electrode layer;
forming a further passivation layer over and in physical contact with an upper surface and with lateral sides of the MTJ/top electrode stack and within the portions of the trench having been reopened, the passivation layer forming and comprising concave structures adjacent to the lateral sides of the MTJ/top electrode stack, wherein the step of forming the further passivation layer is performed after the step of removing portions of the MTJ layer and the top electrode layer to form the MTJ/top electrode stack;
re-forming a top electrode layer over the further passivation layer and over the MTJ/top electrode stack; and
removing portions of the bottom electrode layer, the further passivation layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack, wherein the step of removing portions of the bottom electrode layer, the further passivation layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack is performed after the step of re-forming the top electrode layer, wherein the bottom electrode/MTJ/top electrode stack comprises a spin torque transfer magnetic random access memory (STT-MRAM) structure.

2. The method of claim 1 , wherein forming the trench within the passivation layer comprises forming the trench within a passivation layer comprising a silicon carbide-based passivation material including nitrogen.

3. The method of claim 1 , wherein forming the trench within the passivation layer comprises forming the trench such that an entirety of the trench is over the metallization layer.

4. The method of claim 1 , wherein depositing the bottom electrode layer comprises depositing a layer of a tantalum material.

5. The method of claim 1 , wherein depositing the MTJ layer comprises depositing a pinning layer, a tunnel barrier layer, and a free layer.

6. The method of claim 1 , wherein depositing the top electrode layer comprises depositing a layer of a tantalum material or a titanium material.

7. The method of claim 1 , wherein forming the further passivation layer comprises depositing a non-organic material selected from the group consisting of: un-doped silicate glass (USG), silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof.

8. The method of claim 1 , wherein re-forming the top electrode layer comprises depositing a layer of a tantalum material or a titanium material.

9. The method of claim 1 , further comprising forming a further ILD layer over the STT-MRAM structure.

10. The method of claim 1 , further comprising forming a via to the STT-MRAM structure and a further metallization layer over the via, the via connecting the STT-MRAM structure to the further metallization layer.

11. A method of fabricating an integrated circuit formed on a semiconductor substrate comprising:
forming a bottom electrode segment over a passivation layer, the passivation layer being formed over an interlayer dielectric (ILD) layer and a metallization layer within the ILD layer, the bottom electrode segment being formed off-axis from the metallization layer, wherein forming the bottom electrode segment off-axis over the passivation layer comprises forming the bottom electrode segment such that no part of the metallization layer lies directly underneath the bottom electrode segment when the integrated circuit is viewed in a cross-section taken through a plane perpendicular to a surface of the semiconductor substrate;
depositing a magnetic tunnel junction (MTJ) layer and a top electrode layer over the bottom electrode segment and over the passivation layer;
removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over a portion of the bottom electrode segment, wherein an entirety of the MTJ/top electrode stack lies directly over the bottom electrode segment when the integrated circuit is view in a cross-section taken through the plane perpendicular to the surface of the semiconductor substrate, wherein a width of the MTJ/top electrode stack with respect to a direction parallel to the surface of the semiconductor substrate is less than a width of the bottom electrode segment in the direction parallel to the surface of the semiconductor substrate, and wherein the bottom electrode segment in combination with the MTJ/top electrode stack formed thereover comprises a spin torque transfer magnetic random access memory (STT-MRAM) structure; and
forming a further passivation layer over the bottom electrode segment and along lateral sides of the MTJ/top electrode stack.

12. The method of claim 11 , wherein forming the bottom electrode segment over the passivation layer comprises forming the bottom electrode segment over a passivation layer comprising a silicon carbide-based passivation material including nitrogen.

13. The method of claim 11 , wherein depositing the bottom electrode segment comprises depositing a layer of a tantalum material.

14. The method of claim 11 , wherein depositing the MTJ layer comprises depositing a pinning layer, a tunnel barrier layer, and a free layer.

15. The method of claim 11 , wherein depositing the top electrode layer comprises depositing a layer of a tantalum material or a titanium material.

16. The method of claim 11 , further comprising forming a further ILD layer over the further passivation layer.

17. The method of claim 11 , further comprising forming a first via to the bottom electrode segment of the STT-MRAM structure and a further metallization layer over the via, the first via connecting the STT-MRAM structure to the further metallization layer, and further forming a second via from the further metallization layer to the metallization layer, the second via connecting the further metallization layer to the metallization layer.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Yi Wanbing
• Hong Yang
• Jiang Yi
• Poh Francis
• Chan Tze Ho Simon
• Tan Juan Boon

Classifications

• H01L43/12

  Electricity · mapped topic

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• H01L43/08

  Electricity · mapped topic

• H01L27/222 Primary

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic