Apparatus and method for generating signals for ESD stress testing an electronic device and system for performing an ESD stress test of an electronic device

Patent metadata

Field	Value
Publication number	US-9891268-B2
Application number	US-201514800535-A
Country	US
Kind code	B2
Filing date	Jul 15, 2015
Priority date	Jul 15, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

An apparatus and a method for generating signals for ESD stress testing an electronic device are disclosed. In an embodiment the apparatus is configured to receive a source signal including a source pulse, delay the source pulse to generate a test signal including a test pulse with a pulse width in an ESD time range and generate an auxiliary signal including an auxiliary pulse with a pulse width in the ESD time range.

First claim

What is claimed is:

1. An electrostatic discharge (ESD) stress testing apparatus, the apparatus comprising:
a signal sense circuit configured to receive a source signal comprising a source pulse;
a first delay line coupled to the signal sense circuit and a first input of a device under test (DUT), the first delay line being configured to delay the source pulse to generate a test signal at the first input, wherein the test signal comprises a test pulse with a pulse width in an time range from 1 ns to 1 μs; and
a regulation circuit coupled to the signal sense circuit and a second input of the DUT, the regulation circuit being configured to generate an auxiliary signal at the second input, wherein the auxiliary signal comprises an auxiliary pulse with a pulse width in the time range.

2. The apparatus according to claim 1 , wherein the auxiliary pulse is generated such that the auxiliary pulse rises before a rise of the test pulse and decays after a decay of the test pulse.

3. The apparatus according to claim 1 , wherein the auxiliary pulse is generated such that the auxiliary pulse rises before a rise of the test pulse and decays before a decay of the test pulse.

4. The apparatus according to claim 1 , wherein the auxiliary pulse is generated such that the auxiliary pulse rises after a rise of the test pulse and decays after a decay of the test pulse.

5. The apparatus according to claim 1 , wherein the test pulse is generated with a rise time and a pulse width which respectively deviate from a rise time and a pulse width of the source pulse by not more than 10%.

6. The apparatus according to claim 1 , wherein the regulation circuit is further configured to generate the auxiliary pulse with an amplitude which is independent of an amplitude of the source pulse.

7. The apparatus according to claim 1 , wherein the signal sense circuit is further configured to generate a first sense signal comprising a first sense pulse indicative of a rise and a decay of the source pulse.

8. The apparatus according to claim 1 , wherein the signal sense circuit comprises a resistor.

9. The apparatus according to claim 7 , wherein the signal sense circuit comprises a first power splitter configured to split the source signal into a first fractional signal for generating the test signal and a second fractional signal for generating the first sense signal.

10. The apparatus according to claim 1 , wherein the apparatus further comprises:
a signal processing circuit configured to generate a control signal comprising a control pulse, wherein the signal processing circuit comprises an amplification circuit configured to generate the control pulse with an amplitude that is different from an amplitude of a first sense pulse.

11. The apparatus according to claim 1 , wherein
the signal sense circuit is further configured to generate a second sense signal comprising a second sense pulse which rises after a rise of a first sense pulse of a first sense signal and decays after a decay of the first sense pulse; and
the apparatus further comprises a signal processing circuit coupled to the signal sense circuit and the regulation circuit, the signal processing circuit comprising an OR gate configured to generate a control signal such that the control signal assumes a logical high level when at least one of the first sense signal and the second sense signal assumes a logical high level.

12. The apparatus according to claim 1 , wherein the apparatus further comprises a signal processing circuit coupled to the signal sense circuit and the regulation circuit, the signal processing circuit comprising
a first power splitter configured to split a first sense signal into a first fractional sense signal and a second fractional sense signal,
a second delay line configured to delay the first fractional sense signal and a third delay line configured to delay the second fractional sense signal, and
a second power splitter configured to combine the delayed first fractional sense signal and the delayed second fractional sense signal to form a control signal.

13. The apparatus according to claim 1 , wherein
the signal sense circuit is further configured to generate a second sense signal comprising a second sense pulse which rises after a rise of a first sense pulse of a first sense signal and decays after a decay of the first sense pulse, and
the apparatus further comprises a signal processing circuit coupled to the signal sense circuit and the regulation circuit, the signal processing circuit comprising a comparator configured to compare a control signal such that the control signal assumes a logical high level when at least one of the first sense signal and the second sense signal exceeds a reference voltage.

14. The apparatus according to claim 1 , wherein
the apparatus further comprises a signal processing circuit configured to generate a control signal comprising a control pulse, and
the regulation circuit is further configured to generate the auxiliary signal such that the auxiliary pulse rises and decays synchronously to the control pulse.

15. The apparatus according to claim 1 , wherein the apparatus further comprises:
a signal processing circuit configured to generate a control signal comprising a control pulse; and
a shutdown circuit configured to pull the auxiliary signal to ground after a decay of the control pulse.

16. The apparatus according to claim 15 , wherein the shutdown circuit comprises
a sixth delay configured to generate a shutdown pulse which is delayed with respect to the control pulse,
a transistor configured to pull the auxiliary signal to ground responsive to the shutdown pulse, and
a circuit configured to pull the auxiliary signal to ground for an amount of time which is longer than a width of the shutdown pulse, the circuit comprising a resistor and a capacitor.

17. The apparatus according to claim 1 , wherein:
the first delay line is further configured to delay a first fractional signal to generate the test signal;
the signal sense circuit comprises
a power splitter configured to split the source signal into the first fractional signal and a second fractional signal,
a first resistor configured to sense the second fractional signal and to generate a first sense signal comprising a first sense pulse indicative of a rise and a decay of the source pulse,
a second delay line configured to delay the second fractional signal and to generate a delayed second fractional signal, and
a second resistor configured to sense the delayed second fractional signal and to generate a second sense signal comprising a second sense pulse which rises after a rise of the first sense pulse and decays after a decay of the first sense pulse;

the apparatus further comprises a signal processing circuit coupled to the signal sense circuit and the regulation circuit, the signal processing circuit comprising
an amplification circuit configured to amplify the first sense signal and the second sense signal, and
an OR gate configured to generate a control signal such that the control signal assumes a logical high level when at least one of the first sense signal and the second sense signal assumes a logical high level; and

the regulation circuit is further configured to generate the auxiliary signal such that the auxiliary pulse rises and decays synchronously to a control pulse.

18. An electrostatic discharge (ESD) stress testing method for generating signals for an electronic device, the method comprising:
receiving a source signal comprising a source pulse;
delaying the source

Assignees

• Infineon Technologies Ag

Inventors

• Lebon Julien
• Cao Yiqun
• Glaser Ulrich

Classifications

• G01R31/002

  where the device under test is an electronic circuit · CPC title

• G01R31/2841 Primary

  Signal generators · CPC title