Cancellation of secondary reverse reflections in a very-fast transmission line pulse system

Patent metadata

Field	Value
Publication number	US-9377496-B2
Application number	US-201514870332-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Sep 25, 2012
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.

First claim

What is claimed:

1. A system, comprising:
a very-fast transmission line pulse (VFTLP) system that is configured to:
generate and apply an incident pulse to a device under test (DUT);
generate a delayed replica of the incident pulse; and
cancel a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider,

wherein the power divider is between first and second legs of the VFTLP system;
the first leg is connected to a first port of the power divider, and the second leg is connected to a second port of the power divider, and further comprising a third leg connected to a third port of the power divider; and
the third leg ends in an open circuit termination.

2. The system of claim 1 , wherein the VFTLP system generates the incident pulse using a high voltage power supply, a charge resistor, and a charge line associated with the first leg.

3. The system of claim 1 , wherein the VFTLP system comprises lengths of transmission lines in the first leg, the second leg, and the third leg to maximize a number of reflection cancelations.

4. The system of claim 1 , wherein the VFTLP system comprises lengths of transmission lines in the first leg, the second leg, and the third leg such that an electrical length of the first leg is L, an electrical length of the second leg is L, and an electrical length of the third leg is 2 L.

5. The system of claim 1 , further comprising a respective attenuator connected in series in each of the first leg, the second leg, and the third leg.

6. The system of claim 5 , further comprising:
an N dB attenuator in each of the first, second, and third legs, where N is a first real number greater than zero; and
an N+X db attenuator in the third leg, where X is a second real number greater than zero.

7. The system of claim 1 , wherein the VFTLP system comprises the power divider and the first, second, and third legs connected to the power divider.

8. A system, comprising:
a very-fast transmission line pulse (VFTLP) system that is configured to:
generate and apply an incident pulse to a device under test (DUT);
generate a deli replica of the incident pulse; and
cancel a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider,

wherein the power divider is between first and second legs of the VFTLP system;
the first leg is connected to a first port of the power divider, and the second leg is connected to a second port of the power divider, and further comprising a third leg connected to a third port of the power divider; and
the third lea ends in an open circuit termination;
further comprising a respective attenuator connected in series in each of the first leg, the second leg, and the third leg;
wherein the power divider is a symmetric power divider, and further comprising:
a rise time filter connected in series in the first leg; and
a measuring device connected in series in the second leg.

9. The system of claim 8 , wherein the VFTLP system comprises the power divider and the first, second, and third legs connected to the power divider.

10. A system, comprising:
a very-fast transmission line pulse (VFTLP) system that is configured to:
generate and apply an incident pulse to a device under test (DUT);
generate a delayed replica of the incident pulse; and

cancel a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider,
wherein the VFTLP system comprises:
the power divider;
a high voltage power supply and at least one signal conditioning element in a first leg connected to a first port of a power divider; and
at least one measuring device in a second leg connected to a second port of the power divider, wherein the second leg is configured to be connected to the DUT.

11. The system of claim 10 , wherein the at least one signal conditioning element comprises at least one of:
a high voltage attenuator; and
a rise time filter.

12. The system of claim 10 , wherein the at least one measuring device comprises at least one of:
a sampling device;
an attenuator; and
an oscilloscope.

13. The system of claim 10 , further comprising a third leg connected to a third port of the power divider, wherein the third leg ends in an open circuit termination.

14. The system of claim 13 , wherein the second leg comprises an attenuator connected between the at least one measuring device and the DUT.

Assignees

• IBM

Inventors

• Chang Shunhua T
• Di Sarro James P
• Gauthier Jr Robert J

Classifications

• G01R31/002 Primary

  where the device under test is an electronic circuit · CPC title

• G01R31/2841

  Signal generators · CPC title

• G01R31/2839

  using signal generators, power supplies or circuit analysers (G01R31/2879 takes precedence; multimeters G01R15/12, network analysers G01R27/28) · CPC title