Testing integrated circuits using few test probes

Patent metadata

Field	Value
Publication number	US-9442159-B2
Application number	US-201213716018-A
Country	US
Kind code	B2
Filing date	Dec 14, 2012
Priority date	Mar 5, 2008
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A method of testing integrated circuits, including establishing at least a first physical communication channel between a test equipment and an integrated circuit under test by having at least a first probe of the test equipment contacting a corresponding physical contact terminal of the integrated circuit under test; having the test equipment and the integrated circuit under test exchange, over said first physical communication channel, at least two signals selected from the group including at least two test stimuli and at least two test response signals, wherein said at least two signals are exchanged by means of at least one modulated carrier wave modulated by the at least two signals.

First claim

What is claimed is:

1. A test equipment for testing integrated circuits, comprising:
a first probe adapted to contact a corresponding first contact terminal of an integrated circuit under test for establishing a first physical communication channel between the test equipment and the integrated circuit under test;
a testing circuit electrically connected to said first probe and comprising:
a transmitter circuit configured to simultaneously send to the integrated circuit under test, through the first probe and over said first physical communication channel, two test input stimuli signals using two carrier waves at different frequencies that are respectively modulated by the two test input stimuli signals; and
a receiver circuit configured to receive from the integrated circuit under test two test response signals using two further carrier waves at different frequencies modulated by the two test response signals.

2. The test equipment of claim 1 , wherein the two test response signals are received from the integrated circuit under test over either said first physical communication channel or a second physical communication channel different from the first physical communication channel;
said receiver circuit comprising means for extracting the two test response signals from the modulated two further carrier waves; and
the testing circuit further comprising means for assessing a proper functionality of the integrated circuit based on the extracted two test response signals.

3. The test equipment of claim 2 , wherein the two further carrier waves modulated by the two test response signals are received from the integrated circuit under test over said first physical communication channel.

4. The test equipment of claim 2 , wherein said second physical communication channel comprises a second probe, distinct from said first probe, adapted to contact a corresponding second contact terminal of the integrated circuit under test.

5. The test equipment of claim 1 , comprising:
means for supplying to the integrated circuit under test at least one power supply.

6. The test equipment of claim 5 , wherein said means for supplying comprises a circuit configured to supply the power supply through said first probe combined with said two carrier waves modulated by the two test input stimuli signals.

7. The test equipment of claim 5 , wherein said means for supplying the power supply comprises a second probe adapted to contact a corresponding power supply contact terminal of the integrated circuit under test to supply a first polarity of the power supply through said second probe.

8. The test equipment of claim 7 , wherein said means for supplying the power supply further comprises a third probe adapted to contact a corresponding power supply contact terminal of the integrated circuit under test to supply a second polarity of the power supply to the integrated circuit under test.

9. The test equipment of claim 1 , wherein the integrated circuit under test comprises:
at least one integrated circuit core with said contact terminal adapted to be contacted by said first probe;
a built-in self-test circuit coupled to said at least one integrated circuit core and configured to perform a test based on the test input stimuli signals received from the test equipment.

10. The test equipment of claim 1 , wherein said integrated circuit under test comprises:
means for receiving the two carrier waves modulated by the two test input stimuli signals;
means for extracting the two test input stimuli signals from the modulated two carrier waves; and
means for transmitting the two test response signals using the two further carrier waves modulated by the two test response signals.

11. The test equipment of claim 6 , wherein said integrated circuit under test comprises:
means for separating the power supply from the first physical communication channel.

12. The test equipment of claim 1 , wherein the integrated circuit under test comprises: a three dimensional integrated circuit structure comprising a sequence of stacked semiconductor chips starting from a bottom semiconductor chip and ending at a top semiconductor chip, each semiconductor chip comprising at least one respective integrated circuit, wherein the first probe is adapted to contact the corresponding first contact terminal located on one of the top or bottom semiconductor chips.

13. An apparatus, comprising:
a test equipment;
an integrated circuit under test;
wherein the test equipment comprises:
at least a first probe configured to contact a corresponding physical contact terminal of the integrated circuit under test and form a first physical communication channel; and
a first circuit configured to simultaneously transmit first and second test input stimulus signals through the first probe and over the first physical communications channel to the integrated circuit under test using first and second carrier waves modulated by the first and second test input stimulus signals; and

wherein the integrated circuit under test comprises:
a second circuit configured to perform a test based on the first and second test input stimulus signals received from the test equipment; and
a third circuit responsive to a result of the test performed by the second circuit and configured to transmit a response signal with said result of performing said test over the first physical communication channel and through the first probe to said test equipment using at least a third carrier wave modulated by said first response signal.

14. The apparatus of claim 13 , wherein the integrated circuit under test comprises a three dimensional integrated circuit structure comprising a sequence of stacked semiconductor chips starting from a bottom semiconductor chip and ending at a top semiconductor chip, each semiconductor chip comprising at least one respective integrated circuit, and wherein said physical contact terminal is positioned on one of the bottom or top semiconductor chips.

15. The apparatus of claim 14 , wherein the three-dimensional integrated circuit structure comprises at least one conductive through via crossing the semiconductor chips.

16. The apparatus of claim 13 ,
wherein the first circuit transmits the first and second test input stimulus signals over the first physical communication channel using the modulated first and second carrier waves at a first frequency and a second frequency, respectively; and
wherein the third circuit transmits the first response signal over said first physical communication channel using the modulated second carrier wave at a third frequency.

17. The apparatus of claim 16 , wherein said third frequency is different from the first frequency.

18. The apparatus of claim 16 , wherein the test circuit further comprises:
means for extracting the test response signal from the modulated third carrier wave at the third frequency; and
means for assessing a proper functionality of the integrated circuit under test based on the extracted test response signal.

19. The apparatus of claim 13 , wherein the test equipment further comprises:
a second probe configured to contact a corresponding physical contact terminal of the integrated circuit under test and form a second physical communication channel; and
a fourth circuit configured to transmit a second test input stimulus signal over the second physical communications channel to the integrated circuit under test.

20. The apparatus of claim 13 , wherein the test equipment further comprises means for supplying

Assignees

• St Microelectronics Srl

Inventors

• Pagani Alberto

Classifications

• H10P74/27

  Structural arrangements therefor · CPC title

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H01L2924/1461

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic