Cancellation of secondary reverse reflections in a very-fast transmission line pulse system

Patent metadata

Field	Value
Publication number	US-9274155-B2
Application number	US-201213626372-A
Country	US
Kind code	B2
Filing date	Sep 25, 2012
Priority date	Sep 25, 2012
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.

First claim

What is claimed:

1. A method of cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device under test (DUT) in a semiconductor, the method comprising:
generating an incident pulse in a VFTLP system for applying to the DUT;
generating a delayed replica of the incident pulse; and
cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.

2. The method of claim 1 , further comprising providing the power divider between first and second legs of the VFTLP system.

3. The method of claim 2 , wherein the first leg is connected to a first port of the power divider, and the second leg is connected to a second port of the power divider, and further comprising providing a third leg connected to a third port of the power divider.

4. The method of claim 3 , wherein the generating the incident pulse comprises generating the incident pulse using a high voltage power supply, a charge resistor, and a charge line associated with the first leg.

5. The method of claim 3 , further comprising selecting lengths of transmission lines in the first leg, the second leg, and the third leg to maximize a number of reflection cancelations.

6. The method of claim 3 , further comprising selecting lengths of transmission lines in the first leg, the second leg, and the third leg such that an electrical length of the first leg is L, an electrical length of the second leg is L, and an electrical length of the third leg is 2L.

7. The method of claim 3 , further comprising providing an attenuator in each of the first leg, the second leg, and the third leg.

8. A structure, comprising:
a very-fast transmission line pulse (VFTLP) system for testing an electrostatic discharge (ESD) device under test (DUT), the VFTLP system comprising:
a first leg connected between a power source and a first port of a power divider;
a second leg connected between the DUT and a second port of the power divider;
a third leg connected to a third port of the power divider;
an N dB attenuator in each of the first, second, and third legs, where N is a first real number greater than zero; and
an N+X db attenuator in the third leg, where X is a second real number greater than zero.

9. The structure of claim 8 , wherein the third leg ends in an open circuit termination.

10. The structure of claim 8 , wherein the power divider is a symmetric power divider.

11. The structure of claim 8 , wherein:
the first leg comprises a charge line, a switch, and a first delay line connected in series between a charge resistor and the first port of the power divider;
the second leg comprises a second delay line connected between the DUT and the second port of the power divider; and
the third leg comprises a third delay line connected between an open circuit termination and the third port of the power divider.

12. The structure of claim 8 , wherein:
a total electrical length of the first leg is substantially equal to L;
a total electrical length of the second leg is substantially equal to L; and
a total electrical length of the third leg is substantially equal to 2L.

13. The structure of claim 8 , further comprising:
a rise time filter connected in series in the first leg; and
a measuring device connected in series in the second leg.

14. The structure of claim 8 , wherein the power divider is a 2X dB power divider.

15. A very-fast transmission line pulse (VFTLP) system for testing an electrostatic discharge (ESD) device under test (DUT), the VFTLP system comprising:
a power divider comprising first, second, and third ports;
a charge line, a switch, and a first delay line connected in series between a charging resistor and the first port;
a second delay line connected between the second port and the DUT; and
a third delay line connected between the third port and an open circuit termination,
wherein the power divider, the first delay line, the second delay line, and the third delay line are structured and arranged to cancel a portion of a reverse reflection of an incident pulse by generating a delayed replica of the incident pulse and combining the delayed replica with the reverse reflection at the power divider.

16. The system of claim 15 , wherein:
a total electrical length of a first leg comprising the charge line, the switch, and the first delay line is substantially equal to L;
a total electrical length of a second leg comprising the second delay line is substantially equal to L;
a total electrical length of a third leg comprising the third delay line is substantially equal to 2L.

17. The system of claim 16 , further comprising a respective attenuator connected in series in each of the first leg, the second leg, and the third leg.

18. The system of claim 17 , wherein the power divider is a symmetric power divider, and further comprising:
a rise time filter connected in series in the first leg; and
a measuring device connected in series in the second leg.

Assignees

• IBM

Inventors

• Chang Shunhua T
• Di Sarro James P
• Gauthier Jr Robert J

Classifications

• G01R31/2839

  using signal generators, power supplies or circuit analysers (G01R31/2879 takes precedence; multimeters G01R15/12, network analysers G01R27/28) · CPC title

• G01R31/2841

  Signal generators · CPC title

• G01R31/002 Primary

  where the device under test is an electronic circuit · CPC title