Integrating enhancement mode depleted accumulation/inversion channel devices with MOSFETs

Patent metadata

Field	Value
Publication number	US-9876096-B2
Application number	US-201615336636-A
Country	US
Kind code	B2
Filing date	Oct 27, 2016
Priority date	Dec 10, 2014
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench.
Each gate trench is substantially filled with a conductive material separated from trench walls by a layer of dielectric material to form a gate . A heavily doped well region of a conductivity opposite the first type is provided in the epitaxial region proximate a bottom portion of each of the contact trenches. A horizontal width of a gap between the well region and the gate trench is about 0.05 μm to 0.2 μm.

First claim

We claim:

1. A method, comprising:
forming a plurality of gate trenches into an epitaxial region of a first conductivity type over a semiconductor substrate of the first conductivity type;
substantially filling each trench with a conductive material that is separated from trench walls by a layer of dielectric material to form a gate;
forming one or more contact trenches into the epitaxial region, each contract trench being located between two adjacent gate trenches;
forming a heavily doped well region of a second conductivity type in the epitaxial region opposite to the first conductivity type proximate a bottom portion of each of the one or more contact trenches, wherein a horizontal width between the heavily doped well region and a gate trench of the plurality of gate trenches is about 0.05 μm to about 0.2 μm;
forming one or more heavily doped source regions of the first conductivity type in a top portion of the epitaxial region, each provided between a corresponding one of the contact trenches and a corresponding one of the gate trenches; and
forming a barrier metal over a mesa in a portion of the epitaxial region in which there are no heavily doped source regions, wherein the mesa is formed between two of the contact trenches and two lightly doped regions of the second conductivity type.

2. The method of claim 1 , wherein each gate trench has a gate region in an upper portion of the gate trench and a shield gate region in a lower portion of the gate trench.

3. The method of claim 2 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

4. The method of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

5. The method of claim 1 , further comprising forming one or more lightly doped regions of the second conductivity type are provided in the epitaxial region, wherein the one or more lightly doped regions of the second conductivity type include a particular region formed between one of the heavily doped well regions and one of the gate trenches, wherein the particular region extends to a depth between a bottom portion of the heavily doped well region and a bottom of a nearby one of the contact trenches.

6. The method of claim 1 , wherein the epitaxial region has a doping concentration of about 1e16cm −3 to about 5e16cm −3 .

7. The method of claim 1 , wherein the lightly doped regions of the second conductivity have a doping concentration of about 5e16cm −3 to about 1e17cm −3 .

8. The method of claim 1 , further comprising adjusting a horizontal width of a gap between the heavily doped well region and the gate trench by widening some of the gate trenches.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Bobde Madhur
• Lui Sik
• Yilmaz Hamza
• Kim Jongoh
• Ng Daniel

Classifications

• H01L29/1095

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic

• H01L29/7828

  Electricity · mapped topic

• H01L29/872

  Electricity · mapped topic

• H01L29/66492

  Electricity · mapped topic