Injection control in semiconductor power devices

Patent metadata

Field	Value
Publication number	US-9318587-B2
Application number	US-201414292692-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	May 30, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first buffer layer. An epitaxial layer of the second conductivity type formed above the second buffer layer. A doping concentration of the epitaxial layer is greater than a doping concentration of the second buffer layer. This abstract is provided to allow a searcher or reader to quickly ascertain the subject matter of the disclosure with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

First claim

What is claimed is:

1. A substrate structure, comprising:
a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type;
a semiconductive first buffer layer of the first conductivity type formed above the lightly doped semiconductor substrate, wherein a doping concentration of the first buffer layer is greater than a doping concentration of the lightly doped semiconductor substrate;
a semiconductive second buffer layer of the second conductivity type formed above the first buffer layer; and
a semiconductive epitaxial layer of the second conductivity type formed above the second buffer layer, wherein a doping concentration of the epitaxial layer is greater than a doping concentration of the second buffer layer.

2. The substrate structure of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

3. The substrate structure of claim 1 , further comprising an injection enhancement layer of the second conductivity type formed above the epitaxial layer, wherein a doping concentration of the injection enhancement layer is greater than the doping concentration of the epitaxial layer of the second conductivity type.

4. The substrate structure of claim 1 , further comprising one or more heavily doped regions of the second conductivity type formed through portions of the first buffer layer from the second buffer layer and into corresponding portions of the lightly doped semiconductor substrate.

5. A semiconductor power device, comprising:
a substrate structure comprising a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type;
a semiconductive first buffer layer of the first conductivity type formed above the lightly doped semiconductor substrate, wherein a doping concentration of the first buffer layer is greater than a doping concentration of the lightly doped semiconductor substrate;
a semiconductive second buffer layer of the second conductivity type formed above the first buffer layer; and
a semiconductive epitaxial layer of the second conductivity type formed above the second buffer layer, wherein a doping concentration of the epitaxial layer is greater than a doping concentration of the second buffer layer; and
one or more semiconductor power device structures formed at a top side of the substrate structure.

6. The device of claim 5 , wherein the one or more semiconductor power device structures include one or more trenches formed in the substrate structure, wherein a conductive material is disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches.

7. The device of claim 6 , wherein the one or more semiconductor power device structures further include one or more planar gates each formed over a corresponding trench with an insulation layer provided between each planar gate and corresponding trench.

8. The device of claim 7 , wherein the one or more semiconductor power device structures further include one or more heavily doped contact regions of the second conductivity type, each contact region being surrounded by a corresponding body region of the first conductivity type, wherein the body region is formed in the substrate structure between two neighboring trenches.

9. The device of claim 5 , wherein the one or more semiconductor power device structures includes one or more insulated gate bipolar transistor (IGBT) devices thyristors, MOS-controlled thyristors, or reverse conducting IGBT devices.

10. The device of claim 5 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

11. The device of claim 5 , further comprising an injection enhancement layer of the second conductivity type formed above the epitaxial layer, wherein a doping concentration of the injection enhancement layer is greater than the doping concentration of the epitaxial layer of the second conductivity type.

12. The device of claim 5 , further comprising further comprising one or more heavily doped regions of the second conductivity type formed through portions of the first buffer layer from the second buffer layer and into corresponding portions of the lightly doped semiconductor substrate.

13. A method, comprising:
forming a substrate structure comprising a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type;
forming a semiconductive first buffer layer of the first conductivity type above the lightly doped semiconductor substrate, wherein a doping concentration of the first buffer layer is greater than a doping concentration of the lightly doped semiconductor substrate;
forming a semiconductive second buffer layer of the second conductivity type above the first buffer layer; and
forming a semiconductive epitaxial layer of the second conductivity type above the second buffer layer, wherein a doping concentration of the epitaxial layer is greater than a doping concentration of the second buffer layer.

14. The method of claim 13 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

15. The method of claim 13 , further comprising forming an injection enhancement layer of the second conductivity type above the epitaxial layer, wherein a doping concentration of the injection enhancement layer is greater than the doping concentration of the epitaxial layer.

16. The method of claim 13 , wherein forming a layer of a first conductivity type comprises epitaxially growing the layer of the first conductivity type.

17. The method of claim 13 , wherein forming the first buffer layer comprises blanket implant of first conductivity type dopants in the lightly doped semiconductor substrate.

18. The method of claim 13 , further comprising forming one or more heavily doped regions of the second conductivity type through portions of the first buffer layer from the second buffer layer and into corresponding portions of the lightly doped semiconductor substrate.

19. The method of claim 18 , wherein forming the one or more heavily doped substrate regions of the second conductivity type comprises masked implant of second conductivity dopants into portions of the layer of the first conductivity and lightly doped semiconductor substrate.

20. The method of claim 13 , further comprising forming one or more semiconductor power device structures at a top side of the substrate structure.

21. The method of claim 20 , wherein forming the one or more semiconductor power device structures includes forming one or more trenches in the substrate structure, disposing a conductive material in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches.

22. The method of claim 21 , wherein forming the one or more semiconductor power device structures further includes forming one or more planar gates each over a corresponding trench and providing an insulation layer between each planar gate and corresponding trench.

23. The method of claim 22 , wherein forming the one or more semiconductor power device structures further includes forming one or more heavily doped contact regions of the second conductivity type, wherein each contact region is surrounded by a corresponding body region of the first conductivity type, wherein the body region i

Assignees

• Alpha & Omega Semiconductor

Inventors

• Bobde Madhur
• Hu Jun
• Guan Lingpeng
• Yilmaz Hamza
• Zhang Lei
• Kim Jongoh

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/20

  of semiconductor materials · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title