Integrating enhancement mode depleted accumulation/inversion channel devices with MOSFETs

Patent metadata

Field	Value
Publication number	US-9484452-B2
Application number	US-201414565668-A
Country	US
Kind code	B2
Filing date	Dec 10, 2014
Priority date	Dec 10, 2014
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench. Each gate trench is substantially filled with a conductive material separated from trench walls by a layer of dielectric material to form a gate. A heavily doped well region of a conductivity opposite the first type is provided in the epitaxial region proximate a bottom portion of each of the contact trenches. A horizontal width of a gap between the well region and the gate trench is about 0.05 μm to 0.2 μm.

First claim

We claim:

1. A device, comprising:
a plurality of gate trenches formed into an epitaxial region of a first conductivity type over semiconductor substrate of the first conductivity type, each gate trench being substantially filled with a conductive material that is separated from trench walls by a layer of dielectric material to form a gate;
one or more contact trenches formed into the epitaxial region, each contact trench located between two adjacent gate trenches, wherein a heavily doped well region of a second conductivity type opposite to the first conductivity type is provided proximate a bottom portion of each of the one or more contact trenches and a horizontal width of a portion of the epitaxial region of the first conductivity type between the heavily doped well region and a gate trench of the plurality of gate trenches is from about 0.05 μm to about 0.2 μm; and
one or more heavily doped source regions of the first conductivity type formed in a top portion of the epitaxial region, each provided between a corresponding one of the contact trenches and a corresponding one of the gate trenches; and
a barrier metal formed over a mesa in a portion of the epitaxial region in which there are no heavily doped source regions, wherein the mesa is formed between two of the contact trenches and two lightly doped regions of the second conductivity type.

2. The structure of claim 1 , wherein each gate trench has a gate region in an upper portion of the gate trench and a shield gate region in a lower portion of the gate trench.

3. The structure of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

4. The structure of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

5. The structure of claim 1 , wherein one or more lightly doped regions of the second conductivity type are provided in the epitaxial region, wherein the one or more lightly doped regions of the second conductivity type include a particular region formed between one of the heavily doped well regions and one of the gate trenches, wherein the particular region extends to a depth between a bottom portion of the heavily doped well region and a bottom of a nearby one of the contact trenches.

6. The structure of claim 1 , wherein a threshold voltage for the structure ranges from about 0.2 V to about 0.4 V.

7. The structure of claim 1 , wherein the epitaxial region has a doping concentration of about 1e16 cm −3 to about 5e16 cm −3 .

8. The structure of claim 4 , wherein the lightly doped region of the second conductivity type has a doping concentration of about 5e16 cm −3 to about 1e17 cm −3 .

9. A device, comprising:
a plurality of gate trenches formed into an epitaxial region of a first conductivity type over semiconductor substrate of the first conductivity type, each gate trench being substantially filled with a conductive material that is separated from trench walls by a layer of dielectric material to form a gate;
one or more contact trenches formed into the epitaxial region, each contact trench located between two adjacent gate trenches, wherein a heavily doped well region of a second conductivity type opposite to the first conductivity type is provided proximate a bottom portion of each of the one or more contact trenches and a horizontal width of a gap between the heavily doped well region and a gate trench of the plurality of gate trenches is from about 0.05 μm to about 0.2 μm, wherein the horizontal width of the gap between the heavily doped well region and the gate trench is adjusted by widening some of the gate trenches;
one or more heavily doped source regions of the first conductivity type formed in a top portion of the epitaxial region, each provided between a corresponding one of the contact trenches and a corresponding one of the gate trenches; and
a barrier metal formed over a mesa in portion of the epitaxial region in which there are no heavily doped source regions, wherein the mesa is formed between two of the contact trenches and two lightly doped regions of the second conductivity type.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Bobde Madhur
• Lui Sik
• Yilmaz Hamza
• Kim Jongoh
• Ng Daniel

Classifications

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D8/605

  of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS] · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D84/146

  the built-in components being Schottky barrier diodes · CPC title