Multi-chip package and method of providing die-to-die interconnects in same

Patent metadata

Field	Value
Publication number	US-9875969-B2
Application number	US-201213531827-A
Country	US
Kind code	B2
Filing date	Jun 25, 2012
Priority date	Jun 24, 2009
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A multi-chip package includes a substrate ( 110 ) having a first side ( 111 ), an opposing second side ( 112 ), and a third side ( 213 ) that extends from the first side to the second side, a first die ( 120 ) attached to the first side of the substrate and a second die ( 130 ) attached to the first side of the substrate, and a bridge ( 140 ) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity ( 615, 915 ) in the substrate or between the substrate and a die layer ( 750 ). The bridge may constitute an active die and may be attached to the substrate using wirebonds ( 241, 841, 1141, 1541 ).

First claim

What is claimed is:

1. A multi-chip package comprising:
a substrate having a planar surface without a cavity;
a first die directly electrically attached to the planar surface of the substrate and a second die directly electrically attached to the planar surface of the substrate, the first die and the second die forming a die layer of the multi-chip package, wherein the first die has a back surface substantially co-planar with a back surface of the second die;
a carrier attached to and continuous between the substantially co-planar back surfaces of the first die and the second die, wherein the carrier is not in contact with the substrate; and
a bridge directly electrically attached to the first die and directly electrically attached to the second die and located between the die layer and the planar surface of the substrate, the bridge on the planar surface of the substrate, wherein the bridge is electrically attached to the planar surface of the substrate using a wirebond extending from the bridge in a position between the first die and the second die, wherein:
the first die has a first portion containing a first plurality of interconnect structures, the first plurality of interconnect structures comprising at least three interconnect structures in a first direction and a second portion containing a second plurality of interconnect structures, the second plurality of interconnects structures comprising at least three interconnect structures in a second direction, the second direction orthogonal to the first direction;
the first plurality of interconnect structures has a fine pitch between nearest interconnect structures in the first direction, the first plurality of interconnect structures having a first height;
the second plurality of interconnect structures has a coarse pitch between nearest interconnect structures in the second direction, the coarse pitch larger than the fine pitch, the second plurality of interconnect structures having a second height greater than the first height; and
the first portion is attached to the bridge, and the second portion is attached to the substrate.

2. The multi-chip package of claim 1 wherein: the bridge comprises silicon.

3. The multi-chip package of claim 2 wherein: the bridge is attached to the first die and to the second die using flip-chip connections; the bridge comprises an active die that constitutes a third die of the multi-chip package.

4. The multi-chip package of claim 2 wherein:
the second die has a third portion containing a third plurality of interconnect structures and a fourth portion containing a fourth plurality of interconnect structures;
the third plurality of interconnect structures has the fine pitch;
the fourth plurality of interconnect structures has the coarse pitch; and
the third portion is attached to the bridge.

5. A multi-chip package comprising:
a substrate having a planar surface without a cavity;
a first die directly electrically attached to the planar surface of the substrate and a second die directly electrically attached to the planar surface of the substrate, the first die and the second die forming a die layer of the multi-chip package, wherein the first die has a back surface substantially co-planar with a back surface of the second die;
a carrier attached to and continuous between the substantially co-planar back surfaces of the first die and the second die, wherein the carrier is not in contact with the substrate; and
a bridge comprising silicon directly electrically attached to the first die and directly electrically attached to the second die and located between the die layer and the planar surface of the substrate, the bridge on the planar surface of the substrate, wherein the bridge is electrically attached to the planar surface of the substrate using a wirebond extending from the bridge in a position between the first die and the second die;
the first die has a first portion containing a first plurality of interconnect structures attached to the bridge, the first plurality of interconnect structures comprising at least three interconnect structures in a first direction and a second portion containing a second plurality of interconnect structures attached to the substrate, the second plurality of interconnects structures comprising at least three interconnect structures in a second direction, the second direction orthogonal to the first direction;
the second die has a third portion containing a third plurality of interconnect structures attached to the bridge, the third plurality of interconnect structures comprising at least three interconnect structures in the first direction and a fourth portion containing a fourth plurality of interconnect structures attached to the substrate, the fourth plurality of interconnect structures comprising at least three interconnect structures in the second direction;
the first plurality of interconnect structures and the third plurality of interconnect structures have a fine pitch between nearest interconnect structures in the first direction, the first plurality of interconnect structures and the third plurality of interconnect structures having a first height;
the second plurality of interconnect structures and the fourth plurality of interconnect structures have a coarse pitch between nearest interconnect structures in the second direction, the coarse pitch larger than the fine pitch, the second plurality of interconnect structures and the fourth plurality of interconnect structures having a second height greater than the first height; and
the first plurality of interconnect structures and the third plurality of interconnect structures attached to the bridge.

6. The multi-chip package of claim 5 wherein: the bridge is attached to the first die and to the second die using flip-chip connections; the bridge comprises an active die that constitutes a third die of the multi-chip package.

Assignees

• Braunisch Henning
• Chiu Chia-Pin
• Aleksov Aleksandar
• Lotz Stefanie M
• Swan Johanna M
• Sharan Sujit
• Intel Corp

Inventors

• Braunisch Henning
• Chiu Chia-Pin
• Aleksov Aleksandar
• Lotz Stefanie M
• Swan Johanna M
• Sharan Sujit

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title