Capacitor die embedded in package substrate for providing capacitance to surface mounted die
US-2026018543-A1 · Jan 15, 2026 · US
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Sharan Sujit patents
Sharan Sujit is listed as an inventor on 119 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Sharan Sujit |
| Total patents | 119 |
| First publication | Feb 9, 2016 |
| Latest publication | Jan 15, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
High bandwidth optical interconnection architectures
US-12517314-B2 · Jan 6, 2026 · US
Methods and apparatus to implement a high bandwidth memory (hbm) die
US-2025252073-A1 · Aug 7, 2025 · US
Substrateless double-sided embedded multi-die interconnect bridge
US-12341129-B2 · Jun 24, 2025 · US
Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages
US-2025192017-A1 · Jun 12, 2025 · US
Nested architectures for enhanced heterogeneous integration
US-2025174523-A1 · May 29, 2025 · US
Emib architecture with dedicated metal layers for improving power delivery
US-2025125268-A1 · Apr 17, 2025 · US
Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages
US-12243812-B2 · Mar 4, 2025 · US
Nested architectures for enhanced heterogeneous integration
US-12243806-B2 · Mar 4, 2025 · US
Metal-free frame design for silicon bridges for semiconductor packages
US-2025070056-A1 · Feb 27, 2025 · US
Recent patents
Latest publications not already listed above.
EMIB architecture with dedicated metal layers for improving power delivery
US-12218063-B2 · Feb 4, 2025 · US
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US-2025029908-A1 · Jan 23, 2025 · US
Multi-chip package and method of providing die-to-die interconnects in same
US-2024429173-A1 · Dec 26, 2024 · US
Metal-free frame design for silicon bridges for semiconductor packages
US-12170253-B2 · Dec 17, 2024 · US
Nested architectures for enhanced heterogeneous integration
US-12142545-B2 · Nov 12, 2024 · US
Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
US-12142553-B2 · Nov 12, 2024 · US
Multi-chip package and method of providing die-to-die interconnects in same
US-12113026-B2 · Oct 8, 2024 · US
Interconnect bridge circuitry designs for integrated circuit package substrates
US-2024332193-A1 · Oct 3, 2024 · US
Capacitor die embedded in package substrate for providing capacitance to surface mounted die
US-2024321785-A1 · Sep 26, 2024 · US
Metal-free frame design for silicon bridges for semiconductor packages
US-12074121-B2 · Aug 27, 2024 · US
Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and cost
US-12057413-B2 · Aug 6, 2024 · US
Capacitor die embedded in package substrate for providing capacitance to surface mounted die
US-12046568-B2 · Jul 23, 2024 · US
Silicon groove architectures and manufacturing processes for passive alignment in a photonics die
US-12044888-B2 · Jul 23, 2024 · US
Nested architectures for enhanced heterogeneous integration
US-2024128162-A1 · Apr 18, 2024 · US
Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages
US-2024071884-A1 · Feb 29, 2024 · US
Multi-chip package and method of providing die-to-die interconnects in same
US-2024038671-A1 · Feb 1, 2024 · US
Multi-chip package and method of providing die-to-die interconnects in same
US-11876053-B2 · Jan 16, 2024 · US
Interconnect bridge with similar channel lengths
US-2024006323-A1 · Jan 4, 2024 · US
Layer selection for routing high-speed signals in substrates
US-2024006286-A1 · Jan 4, 2024 · US
Nested architectures for enhanced heterogeneous integration
US-2023411245-A1 · Dec 21, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 119 |
| Braunisch Henning | 1 |
| Chiu Chia-Pin | 1 |
| Aleksov Aleksandar | 1 |
| Lotz Stefanie M | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/724 | 103 |
| H10W90/00 | 102 |
| H10W70/65 | 96 |
| H10W70/611 | 83 |
| H10W70/618 | 74 |