Stress memorization techniques for transistor devices
US-2015364570-A1 · Dec 17, 2015 · US
Method for manufacturing semiconductor structure
US9202913B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9202913-B2 |
| Application number | US-201113133120-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 25, 2011 |
| Priority date | Sep 30, 2010 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
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Abstract
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The present application discloses a method for manufacturing a semiconductor structure, comprising the steps of: a) providing a p-type field effect transistor; b) forming a tensile-stressed layer on the p-type field effect transistor; c) removing a portion of the tensile-stressed layer, so that the remaining portion of the tensile-stressed layer generates compressive stress in the channel of the p-type field effect transistor; and d) performing annealing, so as to achieve the object of memorizing compressive stress in a channel of a transistor and improving the performance of the transistor. The method according to the present invention memorizes the compressive stress in the channel of the transistor by a stress memorization technique, increases mobility of holes, and improves overall performance of the semiconductor structure.
First claim
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The invention claimed is: 1. A method for manufacturing a semiconductor structure, comprising: a) providing a p-type field effect transistor comprising source and drain regions; b) forming a tensile-stressed layer on the p-type field effect transistor; c) removing a portion of the tensile-stressed layer so that the remaining portion of the tensile-stressed layer has edges between the p-type field effect transistor and shallow trench isolations, and generating compressive stre…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9202913B2 cover?
- The present application discloses a method for manufacturing a semiconductor structure, comprising the steps of: a) providing a p-type field effect transistor; b) forming a tensile-stressed layer on the p-type field effect transistor; c) removing a portion of the tensile-stressed layer, so that the remaining portion of the tensile-stressed layer generates compressive stress in the channel of th…
- Who is the assignee on this patent?
- Zhu Huilong, Inst Of Microelectronics Cas
- What technology area does this patent fall under?
- Primary CPC classification H10D30/796. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).